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An Improved “Soft” eFPGA Design and Implementation Strategy
Victor Aken’Ova, Guy Lemieux, Resve Saleh SoC Research Lab, University of British Columbia Vancouver, BC Canada
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Overview Introduction and Motivation Embedded FPGA (eFPGA)
Soft Embedded FPGAs Configurable Architecture Improving Soft eFPGAs Tactical Standard Cells Structured eFPGA layout Results Summary and Conclusions
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Introduction Software Flexibility Hardware Flexibility eFPGAs
SoC designs are getting more complex and costly Programmability can be built into SoCs to amortize costs by reducing chip re-spins Software Flexibility No Flexibility Hardware Flexibility eFPGAs
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Applications for eFPGA Fabrics
CPU An eFPGA for CPU acceleration 3 1 2 eFPGA for product differentiation An eFPGA for revisions
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Motivation shortcomings of existing eFPGA design approaches
Hard eFPGA Highly efficient full-custom layouts but inflexible Soft eFPGA Very flexible but inefficient standard cell layouts alternative approach: flexible + efficient
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“Hard” eFPGA Approach with a library of 3 Cores
user circuit 1 RTL ? ? ? 3 2 Restrictive! overcapacity increases area and delay overheads
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The “Soft” eFPGA Approach
eFPGA RTL Generator auto generated eFPGA ASIC flow much less logic and routing overcapacity Generic Standard Cells 7x area and 2x delay versus full-custom
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Some Solutions to Problems of Existing Approaches
retain eFPGA generator idea for flexibility But… use tactical cells to reduce area + delay use structured approach for efficiency
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Our Improved Design Approach “Soft++”
eFPGA RTL Generator auto generated eFPGA Structured ASIC FLOW GOAL Tactical +Generic Cells combine best of soft and hard approaches
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Island-style eFPGA Architecture
used island-style architecture because Mainstream: existing FPGA CAD tools can can be leveraged can exploit its regular structure to improve design efficiency Created parameterized eFPGA in VHDL
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Island-style eFPGA Architecture
L: Left Edge TILE C C: Corner TILE B B: Bottom Edge TILE (a) Island-style eFPGA (b) eFPGA Tile Layout
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Unstructured vs. Structured eFPGA Design Approach
Soft eFPGA Fixed Logic tile1 tile2 tile3 tile4 (a) unstructured eFPGA layout (b) structured eFPGA layout
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Measured Impact of Structure on eFPGA Quality
Significant improvements in logic capacity result of a more efficient CAD methodology wire-only critical path delay less by 21% Cut CAD design time by as much as 6X
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Architecture-specific Tactical Cells – The Concept
improve quality by creating few tactical standard cells to replace generic cells detailed analysis of design profile should reveal areas that yield significant gains
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Standard cell Area Breakdown for Island-Style Architecture
switch 16% other 12% LUT 30% input mux 13% muxes 42% flip-flops 46% LUT mux 39% flip-flops and multiplexers dominate eFPGA area
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Architecture-specific Tactical Cells – Flip-Flop vs. SRAM
~2:1 area ratio! (a) typical D flip-flop (b) typical SRAM cell An SRAM circuit has fewer transistors = less area
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Custom Layout of Standard Cell – Flip-Flop vs. SRAM
2.5X vdd gnd 1X vdd gnd Standard Cell Flip-flop Tactical SRAM Cell
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Architecture-specific Tactical Cells – CMOS vs. Pass Gate
D O S0 C B A S1 O S0 D C B A VDD S1 after extra output inverter decompose into NAND, INV ~4:1 area ratio! pass tree logic uses fewer transistors and is faster
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Layout Technique for Pass-Tree Multiplexers
vdd n-well n-well vdd n-well cutout gnd extra NMOS (denser cell) gnd underutilized region n-well cut-outs allow denser pass transistor tree layouts
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Architecture-specific Tactical Cells – Cell Area
Equivalent Standard cell Area (um2) Custom Tactical cell Area (um2) improvement Factor Cell 61 1-SRAM 24 2.5 899 146 6.1 16:1 MUX 2228 32:1 MUX 293 7.6 4-LUT 1875 530 3.5 5-LUT 4180 1061 3.9
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Area Impact of Tactical Standard Cells – eFPGA Area
-58% eFPGA -85% (a) soft (b) soft ++ (c) full-custom soft ++ ~2.4X smaller than soft = 58% area savings
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Graphs of Area and Delay Savings
2.4X Better Area 1.6 – 2.8X full-custom area Benchmarks 1.4X Better Delay 1.1X of full-custom delay Benchmarks
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Fabricated Chip Designs with eFPGAs (180nm process)
(a) gradual architecture (b) island-style architecture
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Summary eFPGA area improved 58% (on average)
2 to 2.8X larger than full-custom equivalent (worst case) eFPGA delay improved 40% (average) within 10% of delay of full-custom versions exploited the regularity of island-style architecture to increase logic capacity
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End of Talk
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Question and Answer Slide
Soft Soft++ custom hard Area soft++ fills some of performance gap left by hard Logic Capacity
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