1. 312 Mhz 16-Mb Random Cycle Embedded DRAM Macro for Mobile applications A paper by: Fukashi Morishita, Isamu Hayashi, Hideto Matsuoka, Kazuhiro Takahashi, Kuniyasu Shigeta,Takayuki Gyohten, Mitsutaka Niiro, Hideyuki Noda, Mako Okamoto, Atsushi Hachisuka, Atsushi Amo,Hiroki Shinkawata, Tatsuo Kasaoka, Katsumi Dosaka, Kazutami Arimoto, Member, IEEE, Kazuyasu Fujishima,Kenji Anami, Senior Member, IEEE, and Tsutomu Yoshihara, Member, IEEE Presented By: Eric Tramel

2. Features of the Proposed Design  Self-adjusting Timer Control (STC)  Negative Edge Transmission (NET)  Power-Down Data Retention (PDDR)

3. Self-adjusting Timer Control (STC)‏  Reduces the variance in time delay caused by Process, Voltage, and Temperature (PVT) differences between chips.  Unused during PDDR mode to save on power consumption.  Helps achieve stable random-cycle operation of the DRAM.

4. Negative Edge Transmission (NET)‏  Enables long distance signal transmission from center control blocks to outer local array control blocks.  This scheme is needed because single phase, small pulse width signals get lost in the background for long distance transmissions, thus restricting our physical design.  Allows for consistent timing in each block and accurate control signals to each array, despite varying core capacities.  Transmits control signals as two-phase asynchronous signals.  Only falling edges controlled by NMOS transistors are detected in order to ensure consistent timings.

5. Power-Down Data Retention (PDDR)‏  Allows for decreased power consumption by shutting off non-operating blocks of memory.  Prevents leakage current and unnecessary refreshes.  Decreases overall power consumption by regulating and lowering supply voltages across the chip.  Slower chip control timing for non-clock data retention (and STC shutdown).

6. Design Factoids  Bit Size: 16 Mb  Cell Size: 0.42 x 0.84: 0.35μm²  Feature Size: 0.13μm  Die Size: 13.98mm²  Power Supply: Vddl = 1.2V,Vddh = 2.5V  Error Correction: No  Memory Blocks: 128 Blocks at 128Kb  Cells Per Row: 8  Rows per Block: 128  Cell Construction: MIM, Ta2O5  Refresh Time: 70ms@80°C, 50ms@80°C (PDDR)‏  Bit Line Swing: 1.2V  Bit Line Bias: None