1. 14.2: x86 PC AND INTERRUPT ASSIGNMENT
See the entire interrupt list on page 375 of your textbook.

2. 14.2: x86 PC AND INTERRUPT ASSIGNMENT examining the interrupt vector table
Using DEBUG's dump command to examine the interrupt vector table of a x86 PC, regardless of CPU it contained.

3. 14.2: x86 PC AND INTERRUPT ASSIGNMENT examining the interrupt vector table
From the CS:IP address of the ISR, it is possible to determine which source provides the service.
DOS or BIOS.

4. 14.2: x86 PC AND INTERRUPT ASSIGNMENT analyzing an x86 interrupt service routine
The interrupt 12H service is available on any PC with an x86 microprocessor.
The job of INT 12H is to copy the value of the data area used by BIOS from memory locations 00413H and 00414H into AX and return.
A function of the BIOS POST is to test & count total K bytes of installed conventional RAM, and write it in memory locations 00413H and 00414H
After INT 12H, AX will then contain the total K bytes of conventional RAM memory.

5. Interrupt Service Routine in the IBM PC Technical Reference:
14.2: x86 PC AND INTERRUPT ASSIGNMENT analyzing an x86 interrupt service routine
Interrupt Service Routine in the IBM PC Technical Reference:

6. 14.2: x86 PC AND INTERRUPT ASSIGNMENT INT 12H: checking the RAM size on the PC

7. 14.2: x86 PC AND INTERRUPT ASSIGNMENT INT 12H: checking the RAM size on the PC

8. 14.3: 8259 INTERRUPT CONTROLLER
x86 has only pins INTR & INTA for interrupts.
Figure A Programmable Interrupt Controller

9. 14.3: 8259 INTERRUPT CONTROLLER
The Intel 8259 programmable interrupt controller (PIC) makes expansion of the number of hardware interrupts much easier.
Figure 14-4 Partial Block Diagram of the 8259A

10. 14.3: 8259 INTERRUPT CONTROLLER pins
CAS0, CAS1, and CAS2 - can be used to set up several 8259 chips to expand the number of hardware interrupts to 64.
By cascading 8259 chips in a master/slave configuration.
To use 8259 in slave mode, the chip must be programmed and CAS0 to CAS2 are ignored.
SP/EN, slave programming/enable - in buffered mode, an output signal from 8259 to activate the transceiver (EN).
In nonbuffered mode, an input signal into the 8259.
SP = 1 for the master and SP = 0 for the slave.

11. 14.3: 8259 INTERRUPT CONTROLLER pins
INT - an output connected to INTR of the x86.
INTA - input to the 8259 from INTA of the x86.
IR0 to IR7, interrupt request - hardware interrupts.
When a HIGH is put on any interrupt from IR0 to IR7, 8088/86 will jump to a vector location.
For each IR there exists a physical memory location in the interrupt vector table.
The x86 has 256 hardware or software interrupts. (INT 00–INT FF)

12. 14.3: 8259 INTERRUPT CONTROLLER control words and ports
Figure A Programmable Interrupt Controller
Four control words associated with the 8259:
ICW1 (initialization command word); ICW2; ICW3; ICW4.
There is only one address line A0 to communicate with the chip.

13. 14.3: 8259 INTERRUPT CONTROLLER control words and ports
Table 14-3 and Example 14-7 show the values that A0 and CS must take to initialize the 8259.

14. 14.3: 8259 INTERRUPT CONTROLLER control words and ports
ICW1, initialization command word 1 - functions to make a distinction between ICW2, ICW3, and ICW4 when they are sent to the same address of 8259.
D0, LSB of ICW1, tells 8259 if it should look for ICW4 or not.
If D1 is high, it knows the system is configured in slave mode should not expect any ICW3 in the initialization sequence.
Initialization must always start with ICW1, followed by ICW2, and finally the last one, if needed; there is no jumping ahead.

15. 14.3: 8259 INTERRUPT CONTROLLER control words and ports
ICW1, initialization command word 1.
D2 is always set low (= 0) for x86.
D3 chooses between level triggering or edge triggering of the input signals IR0–IR7.
D4 must always be high.
D5, D6, and D7 are all low for x86 processors.
Figure 14-5 ICW Formats (ICW1 and ICW2)for the 8259

16. 14.3: 8259 INTERRUPT CONTROLLER control words and ports
ICW2, initialization command word 2 - assigns interrupt numbers to IR0–IR7.
The 8-bit INT type number assigned to the corresponding IR0 through IR7 is formed by the lower three bits D3–D7. (T3 through T7)
Lower three bits, D0, D1, and D2, vary from 000 to 111.

17. 14.3: 8259 INTERRUPT CONTROLLER control words and ports
ICW2, initialization command word 2.
D3–D7 can only be programmed according to the assignment of the INT type.
The lower bits are provided by 8259, depending on which interrupt of IR0 to IR7 is activated.
Figure 14-5 ICW Formats (ICW1 and ICW2)for the 8259

18. 14.3: 8259 INTERRUPT CONTROLLER control words and ports
ICW3, initialization command word 3 - used only when two or more 8259s are cascaded.
A single 8259 can be connected to eight slave 8259s.
In cascade mode, there are separate ICW3 words for the master and the slave.
ICW4, initialization command word 4 - D0 indicates the processor mode. (PM)
D0 equals 1 for the 8088/86 and 0 for the 8080/8085.
D1 is AEOI (automatic end of interrupt), is high it eliminates the need for an EOI instruction to be present before the IRET (interrupt return) instruction in the interrupt service routine.

19. 14.3: 8259 INTERRUPT CONTROLLER control words and ports
The 8259 can work in either buffered or nonbuffered mode.
Figure 14-6a & b
ICW Formats (ICW3 and CW4)for the Master & Slave

20. 14.3: 8259 INTERRUPT CONTROLLER control words and ports
SFNM, special fully nested mode must be used when 8259 is in master mode,
Figure 14-6a & b
ICW Formats (ICW3 and CW4)for the Master & Slave

21. 14.3: 8259 INTERRUPT CONTROLLER masking/prioritization IR0–IR7 interrupts
What happens if more than one of interrupts IR0–IR7 is activated at the same time?
Can we mask any of the interrupts?
What about responding to another interrupt while an interrupt is being serviced?

22. 14.3: 8259 INTERRUPT CONTROLLER operation command word OCW
After ICW1, ICW2, and ICW4 have been issued to initialize the 8259, 8088/86 is ready to receive hardware interrupts through 8259's IR0–IR7 pins.
After the process of initialization, the operation command word, OCW, can be sent to mask any of IR0–IR7, or change the priority assigned to each IR.
There are three operation command words: OCW1, OCW2, OCW3.

23. 14.3: 8259 INTERRUPT CONTROLLER operation command word OCW
With the help of OCWs, a programmer can dynamically change the priority associated with each of IR0–IR7, or mask any of them.
Example 14-9 shows how OCWs are sent to the 8259.

24. 14.3: 8259 INTERRUPT CONTROLLER operation command word OCW
Three registers of note in the 8259:
ISR (in-service register)
IRR (interrupt request register)
IMR (interrupt mask register)
Figure 14-4 Partial Block Diagram of the 8259A

25. 14.3: 8259 INTERRUPT CONTROLLER operation command word 1 OCW1
OCW1 is used to mask any of IR0–IR7. Logic 1 is for masking. (disabling)
Logic 0 is for unmasking. (enabling)
Figure 14-7 OCW Format for 8259A

26. 14.3: 8259 INTERRUPT CONTROLLER operation command word 1 OCW1
Figure 14-7 OCW Format for 8259A

27. 14.3: 8259 INTERRUPT CONTROLLER operation command word 2 OCW2
OCW2 - used to assign a specific priority to the IRs.
Fully nested default mode - assigns the highest priority to IR0 and the lowest to IR7.
8259 can be programmed to change the default mode to assign the highest priority to any IR.
Specific rotation mode can be programmed to make rotation follow a specific sequence rather than IR0 to IR7.
The IR served will be stamped as the lowest priority, and will not be served until every other request has had a chance.

28. 14.3: 8259 INTERRUPT CONTROLLER EOI end-of-interrupt command
Assume an 8259, initialized, in the default fully nested mode (IR0 has highest priority; IR7 lowest).
IR3 is activated, and the CPU acknowledges the interrupt by sending back a signal through INTA.

29. 14.3: 8259 INTERRUPT CONTROLLER EOI end-of-interrupt command
Assume an 8259, initialized, in the default fully nested mode (IR0 has highest priority; IR7 lowest).
The CPU goes to the vector table and gets CS:IP of the interrupt service routine and starts to execute the routine.

30. 14.3: 8259 INTERRUPT CONTROLLER EOI end-of-interrupt command
Assume an 8259, initialized, in the default fully nested mode (IR0 has highest priority; IR7 lowest).
Issuing EOI to 8259 indicates IR3 servicing complete, and the bit associated with IR3 in ISR can be reset to zero

31. 14.3: 8259 INTERRUPT CONTROLLER EOI end-of-interrupt command
Assume an 8259, initialized, in the default fully nested mode (IR0 has highest priority; IR7 lowest).
The last three instructions of any interrupt service routine for IR0–IR7 must be issuing the EOI, followed by IRET.

32. 14.3: 8259 INTERRUPT CONTROLLER OCW3
OCW3 is used read 8259 registers IRR (interrupt request register) & ISR (in-service register).
D0 and D1 allow the program to read these registers in order to see which of IR0–IR7 is pending for service and which one is being served.

33. 14.4: USE OF THE 8259 CHIP IN x86 PCs Interfacing 8259 to the IBM PC
Two port addresses must be assigned to the 8259: One for ICW1; the second for ICW2/ICW4.
Since the chip select is activated by Y1 and all the x's for don't care must be zero, the addresses can be calculated in the manner shown.

34. 14.4: USE OF THE 8259 CHIP IN x86 PCs 8259 initialization words in the PC
Configuration for the control words ICW1, ICW2, and ICW4 can be calculated:

35. 14.4: USE OF THE 8259 CHIP IN x86 PCs 8259 initialization words in the PC
PC designers assigned INT 08–INT 0F for expansion of hardware interrupts.
Used by 8259 IR0–IR7, commonly called IRQ0–IRQ7.
INT 08 is for IRQ0, INT 09 is for IRQ1, etc.

36. ICW2 informs 8259 which interrupt numbers are assigned to IRQ0–IRQ7.
14.4: USE OF THE 8259 CHIP IN x86 PCs 8259 initialization words in the PC
ICW2 informs 8259 which interrupt numbers are assigned to IRQ0–IRQ7.
By equating 8259 ICW2 to the interrupt assigned to IRQ0.
ICW2 is the interrupt number for IR0, in the IBM PC, INT08.
The 8259 is only programmed for the value of IRQ0, so the 8259 generates the INT numbers for IR1 through IR7.
ICW3 is used only when multiple 8259 chips are connected in master/slave mode.

37. 14.4: USE OF THE 8259 CHIP IN x86 PCs 8259 initialization words in the PC
ICW4 configuration:
Gives the following code for 8259 initialization:

38. 14.4: USE OF THE 8259 CHIP IN x86 PCs 8259 initialization
Once the 8259 is initialized, it is ready to accept an interrupt on any inputs IRQ0–IRQ7.
Expanding the number of hardware interrupts.
The 8259 is tested by a program in BIOS during the POST (power on self test).

39. Sequence of events after an 8259 IR is activated.
14.4: USE OF THE 8259 CHIP IN x86 PCs sequences of 8259 hardware interrupts
Sequence of events after an 8259 IR is activated.
1. After an IR is activated, the 8259 will respond by putting a high on INTR.
Signaling the CPU for an interrupt request.
/86 puts the appropriate signals on S0, S1 & S2 (S0 = 0, S1 = 0, and S2 = 0), indicating to the 8288 that an interrupt has been requested.
3. The 8288 issues the first INTA to the 8259.
4. The 8259 receives the first INTA and does internal housekeeping, which includes resolution of priority, and resolution of cascading.
5. The 8288 issues the second INTA to the 8259.

40. Sequence of events after an 8259 IR is activated.
14.4: USE OF THE 8259 CHIP IN x86 PCs sequences of 8259 hardware interrupts
Sequence of events after an 8259 IR is activated.
6. On the second INTA pulse, 8259 puts a single interrupt vector byte on the data bus in which 8088/86 will latch. INTR.
The value of the single byte depends on ICW2 and which IR has been activated.
/86 uses this byte to calculate the vector location, which is four times the value of the INT type.

41. Sequence of events after an 8259 IR is activated.
14.4: USE OF THE 8259 CHIP IN x86 PCs sequences of 8259 hardware interrupts
Sequence of events after an 8259 IR is activated.
/86 pushes the flag register onto the stack, clears IF (Interrupt Flag) & TF (Trap Flag), disabling further external interrupt requests and single-step mode. INTR.
And pushes the present CS:IP registers onto the stack.
9. The 8088/86 reads CS:IP of the interrupt service routine from the vector table and begins execution of the interrupt routine.

42. 14.4: USE OF THE 8259 CHIP IN x86 PCs sources of hardware interrupts
With the 8259, the PC has eight interrupts.
IR0 to IR7, plus NMI of the 8088/86.
IBM has used two for internal use by the system.
IR0 - for channel 0 of the 8253 timer to update the time of day (TOD) clock,
IR1 - dedicated to the keyboard.
IR2 through IR7 are available through the expansion slots.
The following interrupts are used on the motherboard:
INT 08 IRQ0 Channel 0 of 8253 timer to update TOD
INT 09 IRQ1 Keyboard input data

43. 14.4: USE OF THE 8259 CHIP IN x86 PCs sources of hardware interrupts
Figure 14-9 PC Sources of Hardware Interrupts

44. 14.4: USE OF THE 8259 CHIP IN x86 PCs sources of NMI
The NMI, nonmaskable interrupt, is a CPU pin, and cannot be masked (disabled) by software.
There are three sources of activation of the NMI:
1. NPIRQ. (numerical processor interrupt request)
2. Read/write PCK. (parity check)
3. IOCHK. (input/output channel check)
The PC recognizes which of interrupt requests has been activated by checking input port C of the 8255.

45. 14.4: USE OF THE 8259 CHIP IN x86 PCs sources of NMI
NMI is masked by a RESET signal from the CPU with CLR of the D flip-flop when the computer is turned on.
Figure Sources of NMI in the PC

46. 14.5: MORE ON INTERRUPTS IN x86 PCs x86 PC hardware interrupts
When the first PC was introduced, six hardware interrupts, IRQ2–IRQ7, were available through the 8-bit section of expansion slot.
IRQ0 and IRQ1, were used by the motherboard.
With the introduction of the based PC AT, another eight interrupts, IRQ8–IRQ15, were added.
In the second generation, designers had to ensure it was compatible with the 8088-based original PC.
Leading to use of IRQ0 & IRQ1 for the system timer and keyboard.

47. 14.5: MORE ON INTERRUPTS IN x86 PCs x86 PC hardware interrupts
IBM made the first 8259 a master, and added the second 8259 in slave mode.
Connecting INT pin of the slave 8259 to IRQ2 of the master 8259.
The master and slave 8259s communicate with each other through pins IRQ2, INT, CAS0, CAS1, and CAS2.

48. 14.5: MORE ON INTERRUPTS IN x86 PCs x86 PC hardware interrupts
On the ISA expansion slot, IRQ10, IRQ11, IRQ12, IRQ14, & IRQ15 are on the 32-pin section.

49. 14.5: MORE ON INTERRUPTS IN x86 PCs x86 PC hardware interrupts
On the ISA expansion slot, IRQ9, IRQ3, IRQ4, IRQ5, IRQ6 & IRQ7 are on the 62-pin section.

50. 14.5: MORE ON INTERRUPTS IN x86 PCs x86 PC hardware interrupts
Figure Chips in Master/Slave Relation for 286 and x86 PCs

51. 14.5: MORE ON INTERRUPTS IN x86 PCs x86 generated interrupts (exceptions)
Intel left the first 32 interrupts (INT 00 to INT 1FH) reserved for future microprocessors.
Designers of the first PC ignored this & assigned many of them to system hardware/software interrupts.
By not adhering to Intel's specifications, IBM has created a massive headache for software designers of protected mode 386 and later systems.

52. 14.5: MORE ON INTERRUPTS IN x86 PCs x86 generated interrupts (exceptions)
Intel continued to assign processor exception cases to INT 5 and higher with each new x86.
See the entire assignment chart on page 396 of your textbook.

53. 14.5: MORE ON INTERRUPTS IN x86 PCs interrupt priority
Resolution of priority among IRQs is up to the 8259.
If both NMI & INTR are activated at the same time, NMI is first since NMI has a higher priority than INTR.
For the IRQs coming through INTR, the 8259 resolves priority depending on the way the 8259 is programmed.
In the x86, IRQ0 has the highest priority & IRQ7 is assigned the lowest priority.

54. 14.5: MORE ON INTERRUPTS IN x86 PCs interrupt priority
Since IRQ8 to IRQ15 of the slave 8259 are connected to IRQ2 of the master 8259, they have higher priority than IRQ3 to IRQ7 of the master 8259.

55. 14.5: MORE ON INTERRUPTS IN x86 PCs level-triggered mode
In level triggered mode, 8259 will recognize a high on the IRQ input as an interrupt request.
The request must remain high until the first INTA is acknowledged from the 8259.
If the IRQ input remains high after the end of interrupt (EOI) command has been issued, the 8259 will generate another interrupt on the same IRQ input.

56. 14.5: MORE ON INTERRUPTS IN x86 PCs edge-triggered mode
In edge-triggered mode, 8259 will recognize an interrupt request only when a low-to-high pulse is applied to an IRQ input.
After the low-to-high transition on the IRQ input, 8259 will acknowledge the interrupt request by activating INTA.
The IRR latch is disabled after the request is acknowledged, and will not latch another interrupt until that IRQ input goes back to low.
A disadvantage of edge-triggered mode is false interrupt caused by a spikes as a result of noise on the IRQ line—especially in high-speed systems.

57. Dec Hex Bin
14 E
ENDS ; FOURTEEN