1. Performed by: Yulia Okunev Instructor: Yossi Hipsh המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory הטכניון - מכון טכנולוגי לישראל הפקולטה להנדסת חשמל Technion - Israel institute of technology department of Electrical Engineering דו ” ח סיכום פרויקט - סופי Developing fast clock source with deterministic jitter חורף 2015 1

2. Abstract המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 2 Designing fast clock source with deterministic jitter for high speed phenomena experiment. Part A: Studying the theory and performing simulation Part B: Building an engineering models and designing the PCB

3. System description המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 3 Engineering model to function as a 4 times faster clock source with deterministic jitter for Jitter phenomena experiment Engineering model to function as “delays array bank”, which divides the clock source into four routes, which feed 4 consumers with clock signals. This clock signals arrive within predetermined skew intervals. This unit will be used for skew phenomena experiment. Printed circuit board which will be used to create 8 times faster clock source

4. Specification המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory Hardware: Power Divider - ZN4PD1-50-S+ mini-Circuits Power Combiner - ZN4PD1-50-S+ mini-Circuits Coaxial cables Software : Simulation- SigXplorer Schematic – Orcad (Cadence) Layout – PCB designer (Cadence) 4

5. System Block Diagram המעבדה למערכות ספרתיות מהירות High speed digital systems laboratory 5