1. 19 Nov 2014 1 SPP-FIELDS Antenna Electronics Board (AEB) CDR Peer Review J. W. Bonnell, D. N. Seitz Space Sciences Laboratory UC Berkeley jbonnell@ssl.berkeley.edu dseitz@ssl.berkeley.edu

2. 19 Nov 2014 Work Since PDR, Work To Be Done Interim CogE split between is Bonnell and Seitz (Mar 2014, Heavner’s departure for ICON). New staffing has tightened up collaboration with PA design effort (Seitz, Bonnell, Goetz) and kept relevant interfaces (power, signal, noise) consistent and well-understood (work load is high, however). EM design, schematics, layouts finalized, reviewed, fabricated, assembled (1x AEB1; 2x AEB2), and functionally tested: –Bench and INT configs. –DC and AC sweeps at bench test level. –End-to-end analog input to digital output (Science and HSK). –Sensor bias control and readback (Science and HSK time series). –PA+AEB1+RFS-Analog (noise floor and power supply lines). Still to come before FM fabrication: –Thermal testing PA+AEB1 – noise, bandwidth, calibration changes. –TVAC testing MEP thermal tests to establish board ops temperature ranges. Support of PA/V5 TVAC testing –Final Parts approvals (MAX256, Single Event Transients) 2

3. 19 Nov 2014 SPP FIELDS PA 3

4. 19 Nov 2014 LF Section Details: Bootstrap 4

5. 19 Nov 2014 5 LF Section Details: Biasing

6. 19 Nov 2014 Scope of AEB Design Effort Antenna Electronics Board (AEB, see following block diagram slide) –Full AEB functionality split into two boards: AEB1 (V1, V2, V5) – primarily controlled by DCB. AEB2 (V3, v4) – primarily controlled by TDS. –FGND Driver: 1 channel each for 4 forward whips (V1..4). 1 channel for aft antenna (V5). –Sensor bias current, Stub and Shield bias voltage drivers: 3 channels of each for V1..4. Sensor bias current and “Box” bias voltage driver for subset for aft whip or dipole. –Sensor preamp bias range relay control: 1 channel each for 4 forward whips (3 ranges). one for V5. –Floating Power Supplies: 2 floaters to support opposing pairs of forward whips. 1 floater to support aft whip or dipole (AEB1 only). –V5 Preamp Power and Heater Control: FSW-controlled floating power supply and pre-heater resistor. –HF Output Stage Power Regulation: +/- 6V from LVPS1/2 regulated down to +/- 5V for wide (4x) current consumption (signal amplitude). –Passthrough of LF signal to DFB. –Serial Command and Data (HSK) I/F to DCB/TDS. 6

7. 19 Nov 2014 AEB1 BLOCK DIAGRAM 7

8. 19 Nov 2014 AEB 2 BLOCK DIAGRAM 8

9. 19 Nov 2014 AEB Requirements (stable since Dec 2012) Preamp signal characteristics –DC voltage level: ± 60Vdc w.r.t. AGND (± 60 Vdc at full bias offsets; up to +/- 100Vdc at reduced bias current and voltage levels). –AC voltage level: ± 10V w.r.t. floating ground up to 70 kHz (± 13V capability up to several 100 kHz) Floating Ground Driver –Input: LF Preamp signal –Input filter roll off: 500 Hz (~450 Hz actual, soft requirement due to limited AC dynamic range). –Output voltage level: ± 60Vdc w.r.t. AGND –Floating supply rails: ± 15Vdc. Bias, Stub, Shield Drivers (Bias and Box on V5) –Reference Input: LF Preamp signal –Reference input filter roll off: 500 Hz (~450 Hz actual, match FGND) –Output voltage level: Vref ± 40Vdc (max, programmable) w.r.t. AGND –DAC resolution: 12-bit (~.025%). Noise voltages at Bias, Stub, and Shield outputs consistent with noise floor requirements, downstream filtering and processing, and predicted coupling to antenna (TBD). 9

10. 19 Nov 2014 AEB Requirements, con’t. Bias, Stub, Shield Drivers (Bias and Box on V5) – Output Currents –Bias ranges (AEB+PA, V5 is lowest range only): +/- 802 nA (360 nA CBE @ 1 AU). +/- 14 uA (0.25 AU). +/- 414 uA (184 uA CBE @ 9 Rs). –PA1..4 Stub and Shield Currents (max is photoelectron-dominated): Stub:60 nA (1 AU), 30 uA (9.5 Rs, nominally shadowed!). Shield:200 nA (1 AU), 100 uA (9.5 Rs). –V5 Box Currents (nominally shadowed; max is photelectron-dominated): Box:~40 nA (1 AU). –Sunlit surfaces dominated by photoelectron and possibly thermionic electron emission, and so currents tend to be sinking of current from exposed surfaces (sourcing e- to surfaces consistent with sheath I-V curves). 10

11. 19 Nov 2014 AEB 1 POWER BLOCK DIAGRAM 11 NOTES: 1.Ignore current estimates on this diagram – OBSOLETE. 2.Delay is relative to turn on time of 5V Floater primary supply (next slide). 3.+/- 12V, +/- 6V on same delay as +/- 100V.

12. 19 Nov 2014 AEB 1 POWER FLOATING SUPPLY 12

13. 19 Nov 2014 AEB 1 Coax Cable and Connector DIAGRAM 13

14. 19 Nov 2014 All LF HRN Shields tied to AGND rather than mix of AGND and FGND. Regularized input and output timing constants for drivers (FGND, Bias, Stub, Shield all to 450-Hz 3-dB frequency). Replaced HSK MUX (failures of original in UMN EM units) and added 5-to-3.3-V level shift transistors required for digital IF to DCB/TDS. Addressed “0x000” startup state (FS negative) on bias DACs at DCB level (AEB1/2 start up includes setting DACs to mid-scale, 0x7FF). Changed floater transformer winding ratio to accommodate +/- 15-V PA supply rails (legacy design was +/- 10-V). Added 10-kohm series resistors on Floater SYNC inputs to prevent “powered via SYNC” anomaly. Added zeners and transistors to FGND input stage power supply to meet derated max supply voltages on AD648 (to be implemented). Defined all shield connections on PA1, 2, and 5 connectors and harnesses. Added current limit diodes to PA5 power supply relay outputs to protect relay contacts from inrush/outrush currents. Rewired PA5 power supply relay rails to ground rails to FGND via 100-ohm instead of AGND to minimize DC potential difference across relay. 14 Changes to AEB EM During Design, Assembly, and Test

15. 19 Nov 2014 Bench Testing - Setup 15

16. 19 Nov 2014 Bench Testing – Power In (AEB1/SN002) 16

17. 19 Nov 2014 Bench Testing – Floaters (AEB1/SN002) 17

18. 19 Nov 2014 Bench Testing – +/5V Regs (AEB1/SN002) 18

19. 19 Nov 2014 Bench Testing – AC Response (AEB1/SN002, V5) 19 3-dB

20. 19 Nov 2014 Bench Testing – DC Response (AEB1/SN002, PA1) 20

21. 19 Nov 2014 Bench Testing – DC Response, con’t (AEB1/SN002, PA1) 21 Residuals correspond to < 1nA at lowest IBIAS range – AOK.

22. 19 Nov 2014 I&T Testing – Setup (PA+AEB1+DCB+DFB+LNPS1, 31 Oct 2014) 22 Safe-to-Mate. Power Consumption – as expected. LF/MF/HF response check (crude, LF and MF termination off-nominal). PA/AEB Bias ranging and setting (HSK and Science readback) – as expected.

23. 19 Nov 2014 BACKUP SLIDES 23

24. 19 Nov 2014 AEB 2 Coax Cable and Connector Diagram 24

25. 19 Nov 2014 AEB 2 POWER BLOCK DIAGRAM 25

26. 19 Nov 2014 AEB 2 POWER FLOATING SUPPLY 26

27. 19 Nov 2014 PARTS –All parts conditionally approved by Parts Control Board (Nov 2014). –Single-Event Transient (SET) effects analysis on MAX256 to be completed (by I-CDR; no obvious impact from infrequent short transients). 27

28. 19 Nov 2014 I-PDR Peer Review Items (24 Oct 2013) DescriptionOriginatorTypeResponse Put a relay on AEB to turn on and off the heater. See if RC filtering is necessary and look into +/- supply instead of single supply to see if that will reduce possible EMI. K. Hatch (SSL)AdvisoryIndependent relays for V5 PWR and HTR control added; both feed off of floating +/- 15V V5 supply; no additional EMI filters added at this time. Add “on box bias on V5” on chart, level 4 requirement update J. Hoberman (SSL)AdvisoryTo be updated by I-PDR. Remove LF coax requirement from AEB and Redo coax diagram J. Hoberman (SSL)AdvisoryDone; also requirement for all on-PCB coax runs removed. 28

29. 19 Nov 2014 I-PDR Peer Review Items, con’t (24 Oct 2013) DescriptionOriginatorTypeResponse What happens to the output when the sync is removed from AEP? Is it a smooth transition? Test and document. P. Berg (SSL)AdvisoryQuestion raised in I-PDR as well; removal of SYNC disabled MAX256 in Floater supplies; after discusion of risks, MODE drive set to LOW to force external-clock- only operation in EM. Test DAC turn on characteristics when connected to preamp box. What happens when the DAC comes on at 0 volts instead of mid-scale? J. Hoberman (SSL)AdvisoryDone at bench test level – no obvious issues. Will check at INT level as well. Concern about incomplete analysis of the output stage of the floater circuit (Q19, Q20) K. Hatch (SSL)AdvisoryNo further analysis done at this time for legacy design; EM implementation works as expected. 29

30. 19 Nov 2014 HF Section Details: Input Coupling 30

31. 19 Nov 2014 AEB – FGND Bandwidth and LF Dyn Range AEB-31 The FGND bandwidth needs to be higher than one expects to allow for low-distortion measurement of large-amplitude LF fields. The top panel shows a 120-Vpp 100-Hz signal (solid black line) and the response of the Floating Ground Driver (FGND, green dashed) and positive and negative Preamp Floating Supply Rails (red and blue dash-dot). This example is consistent with the initial RBSP-EFW-BEB FGND design and the OP-15 used in the EFW PRE circuit (~2-V headroom on pos and neg supplies to give harmonic amplitudes < -40dB relative to fundamental). The FGND is a one-pole RC low-pass filtered version of the input signal, with corner (3-dB) frequency of 300 Hz (three times the input signal!). The region between the red and blue lines at any give time indicates the range of signal input voltages that will be faithfully reproduced. When the voltage margin on the pos or neg rail goes negative, the output will be distorted by clipping.

32. 19 Nov 2014 AEB – LF->HF Dynamic Range AEB-32 The dynamic range (maximum amplitude signal measured meeting maximum distortion requirements) varies with input frequency: At very low frequencies, the dynamic range is set by the AEB HV output stage rails. At frequencies well above the FGND rolloff, the dynamic range is set by the PRE floating supply rails and the headroom the preamp requires on those rails. At intermediate frequencies, the dynamic range falls off remarkably fast as the rolloff frequency of the FGND is approached. 450 V pp (± 225 V, ~100 V/m), BUT… 26 V pp (± 13 V,~7 V/m) At FGND 3-dB Frequency 500 Hz: 36 V pp (± 18 V, ~9 V/m) Frequency Maximium Amplitude

33. 19 Nov 2014 AEB – LF Response At Different Frequencies AEB-33 Examples using Flight RBSP-EFW AEB and PRE floating supply designs (500-Hz FGND bandwidth). Left plot is threshold case for 100-Hz input frequency (65 V amplitude [130 Vpp]). Right plot is threshold case for 500-Hz input frequency (18 V amplitude [36 Vpp]).

34. 19 Nov 2014 AEB – LF->HF Dynamic Range AEB-34

35. 19 Nov 2014 AEB – Biasing Reduces LF Dynamic Range AEB-35 V_BIAS, V_GUARD, V_STUB, etc. (up to ± 40 V; typ. ≤ ± 20 V). The full HV rail-to-rail voltage is not available to the signal at low frequencies if current and voltage biasing is active and one wants stable DC current and voltage biasing. For typical conditions and designs (current biasing to half possible range, +/- 40 V offset system), this eats up another 20 V or so of the dynamic range in a conservative (worst-case) design. Similarly, any stable SC potential offset (SC floating potential, V SC ) eats up part of the LF dynamic range (few to tens of volts) in a conservative (worst-case) design. Large values of V SC are typically driven by biasing, but will also be driven on SPP by the space charge in the SC wake.