1. Status of the n-XYTER testing Knut Solvag, Gerd Modzel, Christian Schmidt, Markus Höhl, Andrea Brogna, Ullrich Trunk, Hans-Kristian Soltveit CBM

2. DPG Tagung Giessen, Universität Giessen, March 12th – March 16th 2007 n-XYTER The First Dedicated Neutron Detector Readout ASIC Developed within FP6 For thermal neutron applications Is now beeing tested in a cooperation between Heidelberg, DETNI and CBM

3. DPG Tagung Giessen, Universität Giessen, March 12th – March 16th 2007 128 asynchronous analogue inputs at 32 MHz total average input rate 8 LVDS output lines at 4 x 32MHz: time stamp, channel no. + 1 differential, analogue output AMS CMOS 0.35µ with thick metal four 250 dies shared with DETNI collab. n-XYTER: DETNI Neutron Detector Readout ASIC Neutron – X, Y, Time and Energy... R

4. DPG Tagung Giessen, Universität Giessen, March 12th – March 16th 2007 charge preamp FAST shaper 18.5 ns peaking SLOW shaper (2 stages) 140ns peaking time Peak detector & hold, free running comparator Time Walk Compensation circuit PDH reset pulse height output trigger timestamp reg. charge input Data Driven Front-End: Asynchronous Channel Trigger dig. FIFO analogue FIFO  128 channel data driven charge sensitive front-end  Front end for either polarity input signals  Fast charge sensitive pre-amp and peak detector  Time stamping with 1ns resolution  Purely data driven, autonomous hit detection

5. DPG Tagung Giessen, Universität Giessen, March 12th – March 16th 2007 Token Ring Readout Process Analog FIFO Timestamp FIFO data readout bus token cycle  Focus bandwidth where there is data  Automatic zero suppression Disc. token cell control logic for data readout or token pass

6. DPG Tagung Giessen, Universität Giessen, March 12th – March 16th 2007 n-XYTER 1.0 Testboard  64 channels connected  I²C-Interface  Test points accessible  All functional tests possible  All analogue evaluation possible

7. DPG Tagung Giessen, Universität Giessen, March 12th – March 16th 2007 Registers  44 registers in total  Registers are configured by I²C-Bus  16 mask registers for shutting down individual channels  14 adjustment registers for setting voltages/currents in the chip  13 configuration/status registers  1 shift register for local channel threshold trimming

8. DPG Tagung Giessen, Universität Giessen, March 12th – March 16th 2007 First measurement of the Adjustment registers Expected (simulation): range: 0.928 – 1.651 V Measurement: range: 0.880 – 1.655 V

9. DPG Tagung Giessen, Universität Giessen, March12th – March 16th 2007 Analogue Pulses, Peaking Time, Front-End Noise FAST channel (Timing) SLOW channel (Energy) ENC26.9 e/pF + 200 e12.7 e/pF + 233 e peaking time a (1% to 99%) 18.5 ns139 ns 30 pF, giving 1000 (850)e 600 e power consumption: 12.8 mW for one complete channel; OK for neutrons!

10. DPG Tagung Giessen, Universität Giessen, March 12th – March 16th 2007 Test modes Charge injection Test pulse mode  The whole chip can be tested without external input  Size of the input charge can be varied charge preamp FAST shaper 18.5 ns peaking SLOW shaper (2 stages) 140ns peaking time Peak detector & hold, free running comparator Time Walk Compensation circuit PDH reset pulse height output trigger timestamp reg. charge input dig. FIFO analogue FIFO Test pulse modeTest trigger mode  The analog part is completly circumvented Signal injection Test trigger mode

11. DPG Tagung Giessen, Universität Giessen, March 12th – March 16th 2007 Noise of the analog channels Trigger efficiensy of treshold scan Derivative gives image of noise

12. DPG Tagung Giessen, Universität Giessen, March 12th – March 16th 2007 Trigger efficiency for all channels unshielded chip Channel number

13. DPG Tagung Giessen, Universität Giessen, March 12th – March 16th 2007 Trigger efficiency for all channels shielded chip Channel number

14. DPG Tagung Giessen, Universität Giessen, March 12th – March 16th 2007 Summary - Conect to silicon strip, and see wether it operates sattisfactionary with a detector attached - Improve test setup - Quantitative measurement of the analog output -Testing of preformance at higher clock frequencies -Homogeneity of the chip Further testing -Chip is fully functional tested -No flaws surfaced -Analog preformance apears to be to specifications