1. Department of Communication Engineering, NCTU 1 Unit 4 Arithmetic and Logic Units

2. Department of Communication Engineering, NCTU 2 4.1 Serial Adder with Accumulator

3. Hardware Project Unit 4 Arithmetic & Logic Units Sau-Hsuan Wu Department of Communication Engineering, NCTU 3 We design a control circuit for a serial adder with an accumulator

4. Hardware Project Unit 4 Arithmetic & Logic Units Sau-Hsuan Wu Department of Communication Engineering, NCTU 4 Operation

5. Hardware Project Unit 4 Arithmetic & Logic Units Sau-Hsuan Wu Department of Communication Engineering, NCTU 5 State graph for serial adder control

6. Hardware Project Unit 4 Arithmetic & Logic Units Sau-Hsuan Wu Department of Communication Engineering, NCTU 6

7. 7 4.2 A Parallel Multiplier

8. Hardware Project Unit 4 Arithmetic & Logic Units Sau-Hsuan Wu Department of Communication Engineering, NCTU 8 A multiplier for binary positive number Save the product in a register Shift the product to the right each time

9. Hardware Project Unit 4 Arithmetic & Logic Units Sau-Hsuan Wu Department of Communication Engineering, NCTU 9 Datapath of the multiplier

10. Hardware Project Unit 4 Arithmetic & Logic Units Sau-Hsuan Wu Department of Communication Engineering, NCTU 10 Operation for a simple example

11. Hardware Project Unit 4 Arithmetic & Logic Units Sau-Hsuan Wu Department of Communication Engineering, NCTU 11 State graph for a straightforward implementation

12. Hardware Project Unit 4 Arithmetic & Logic Units Sau-Hsuan Wu Department of Communication Engineering, NCTU 12 An alternative approach

13. Hardware Project Unit 4 Arithmetic & Logic Units Sau-Hsuan Wu Department of Communication Engineering, NCTU 13 Operation using a counter

14. Department of Communication Engineering, NCTU 14 4.3 A binary Divider

15. Hardware Project Unit 4 Arithmetic & Logic Units Sau-Hsuan Wu Department of Communication Engineering, NCTU 15 A parallel divider for positive numbers A circuit to divide an 8-bit dividend by a 4-bit divisor to obtain a 5-bit quotient

16. Hardware Project Unit 4 Arithmetic & Logic Units Sau-Hsuan Wu Department of Communication Engineering, NCTU 16 Block diagram  Store the dividend in a register  Shift the dividend to the left each time  An extra bit is required on the left end of the dividend register

17. Hardware Project Unit 4 Arithmetic & Logic Units Sau-Hsuan Wu Department of Communication Engineering, NCTU 17 The operation for an example  Load initial data  Subtraction cannot be carried out without a negative result  Thus, shift the dividend to the left before we subtract

18. Hardware Project Unit 4 Arithmetic & Logic Units Sau-Hsuan Wu Department of Communication Engineering, NCTU 18  The quotient digit of 1 is stored in the unused position of the dividend register  Shift the dividend one place to the left  Shift once again The first quotient digit

19. Hardware Project Unit 4 Arithmetic & Logic Units Sau-Hsuan Wu Department of Communication Engineering, NCTU 19  Subtraction is carried out, and the 3rd quotient digit of 1 is stored in the unused position of the dividend register  A final shift is carried out, and the 4th quotient bit is set to zero What if the quotient is too large > 4 bits  If the initial left five bits  the divisor  overflow

20. Hardware Project Unit 4 Arithmetic & Logic Units Sau-Hsuan Wu Department of Communication Engineering, NCTU 20 Datapath

21. Hardware Project Unit 4 Arithmetic & Logic Units Sau-Hsuan Wu Department of Communication Engineering, NCTU 21 The state graph  If X 8 X 7 X 6 X 5 X 4  Y 3 Y 2 Y 1 Y 0  C =1  Sh and Sub and the quotient bit is 1  Otherwise  Sh and the quotient bit is 0

22. Hardware Project Unit 4 Arithmetic & Logic Units Sau-Hsuan Wu Department of Communication Engineering, NCTU 22 Implementation with the one-hot assignment