1. Combinational Circuitsby
Dr. Amin Danial Asham

2. References
Digital Design 5th Edition, Morris Mano

3. INTRODUCTION
Logic circuits for digital systems may be combinational or sequential.
A combinational circuit consists of logic gates whose outputs at any time are determined from only the present combination of inputs.
In contrast, sequential circuits employ storage elements in addition to logic gates.
A combinational circuit consists of input variables, logic gates, and output variables.
Combinational Logic gates react to the values of the signals at their inputs and produce the value of the output signal, transforming binary information from the given input data to a required output data.
The diagram of a combinational circuit has logic gates with no feedback paths or memory elements. A feedback path is a connection from the output of one gate the input of a second gate that forms part of the input to the first gate.

4. INTRODUCTION (continue)
A block diagram of a combinational circuit with n input binary variables come from an external source; the m output variables are produced by the internal combinational logic circuit and go to external destination.
For n input variables, there are 2n possible binary input combinations.
For each possible input combination, there is one possible output value.

5. INTRODUCTION (continue)
Thus, a combinational circuit can be specified by a truth table that lists the output values for each combination of input variable.
Example: The following truth table describes a combinational circuit with n=2, and m=2.
A combination circuit also can be described by m Boolean function. One for each output variable. Each function is expressed in terms of the n input variables.
𝑓 1 = 𝑥 1 ′ 𝑥 2 ′ and 𝑓 2 = 𝑥 1 𝑥 2 ′
𝑥 1
𝑥 2
𝑓 1
𝑓 2 1

6. ANALYSIS PROCEDURE
The analysis of a combinational circuit requires that we determine the function that the circuit implements.
To obtain the output Boolean functions from a logic diagram, we proceed as follows:
Label all gate outputs that are a function of input variables with arbitrary symbols-but with meaningful names. Determine the Boolean functions for each gate output.
Label the gates that are a
function of input variables
and previously labeled gates
with other arbitrary symbols.
Find the Boolean functions
for these gates.
Repeat the process outlined in
step 2 until the outputs of the
circuit are obtained.
By repeated substitution of
previously defined functions,
obtain the output Boolean
functions in terms of input
variables.

7. ANALYSIS PROCEDURE (continues)
𝐹 2 =𝐴𝐵+𝐴𝐶+𝐵𝐶
𝑇 1 =𝐴+𝐵+𝐶
𝑇 2 =𝐴𝐵𝐶
𝑇 3 = 𝐹 2 ′ 𝑇 1
𝐹 1 = 𝑇 2 + 𝑇 3
=𝐴𝐵𝐶+ 𝐹 2 ′ 𝑇 1
=𝐴𝐵𝐶+ 𝐴𝐵+𝐴𝐶+𝐵𝐶 ′ 𝐴+𝐵+𝐶
=𝐴𝐵𝐶+ 𝐴𝐵 ′ 𝐴𝐶 ′ 𝐵𝐶 ′ 𝐴+𝐵+𝐶
=𝐴𝐵𝐶+ 𝐴 ′ + 𝐵 ′ 𝐴 ′ + 𝐶 ′ 𝐵 ′ + 𝐶 ′ 𝐴+𝐵+𝐶
=𝐴𝐵𝐶+ 𝐴 ′ + 𝐴 ′ 𝐶 ′ +𝐴′ 𝐵 ′ + 𝐵 ′ 𝐶 ′ 𝐴 𝐵 ′ + 𝐵 ′ 𝐶+ 𝐴𝐶 ′ + 𝐵𝐶 ′
=𝐴𝐵𝐶+ 𝐴 ′ 1+ 𝐶 ′ + 𝐵 ′ + 𝐵 ′ 𝐶 ′ 𝐴 𝐵 ′ + 𝐵 ′ 𝐶+ 𝐴𝐶 ′ + 𝐵𝐶 ′
=𝐴𝐵𝐶+( 𝐴 ′ + 𝐵 ′ 𝐶 ′ ) 𝐴 𝐵 ′ + 𝐵 ′ 𝐶+ 𝐴𝐶 ′ + 𝐵𝐶 ′
=𝐴𝐵𝐶+ 𝐴 ′ 𝐵 ′ 𝐶+ 𝐴 ′ 𝐵𝐶 ′ +𝐴 𝐵 ′ 𝐶 ′

8. ANALYSIS PROCEDURE (continues)
To obtain the truth table directly from the logic diagram without going through the derivation of the Boolean functions, we proceed as follows:
Form 2 𝑛 possible input combinations from n inputs
Label the outputs of selected gates.
Obtain the truth table for the outputs of those gates which are functions of the in put variables only.
Proceed to obtain the truth table of outputs of those e gates which are a function of previously defined values
until all outputs are determined.

9. The procedure involves the following steps:
DESIGN PROCEDURE
The design of combinational circuits starts from the specifications of the design objectives to obtain the logic circuit diagram or a set of Boolean functions from which the logic diagram can be obtained.
The procedure involves the following steps:
Determine the required inputs and outputs and assign a symbol to each.
Drive the truth table that defines the required relationship between inputs and outputs.
Obtain the simplified Boolean functions for each output as a function of the input variables.
Draw the logic diagram and verify the correctness of the design.

10. DESIGN PROCEDURE (continue)
Code Conversion from BCD to Excess-3 code
A Code converter converts from binary code A to binary code B. The input line must supply the bit combinations of elements as specified by code A and the output lines must generate the corresponding bit combination of code B
To design a converter that converts from BCD code to Excess-3 code, we starts with the truth table of the converter.
BCD code and Excess-3 code are both 4 bits, therefore the converter has 4 inputs and 4 outputs. where A,B,C, and D are the inputs and w,x,y, and z are the outputs.

11. DESIGN PROCEDURE (continue)
Code Conversion from BCD to Excess-3 code (continue)
Using the maps to drive the simplified Boolean function for the each output, we get for the output z
𝒎 𝟎
𝒎 𝟏
𝒎 𝟐
𝒎 𝟑
𝒎 𝟒
𝒎 𝟓
𝒎 𝟔
𝒎 𝟕
𝒎 𝟖
𝒎 𝟗

12. DESIGN PROCEDURE (continue) For the output y
Code Conversion from BCD to Excess-3 code (continue)
For the output y
𝒎 𝟎
𝒎 𝟏
𝒎 𝟐
𝒎 𝟑
𝒎 𝟒
𝒎 𝟓
𝒎 𝟔
𝒎 𝟕
𝒎 𝟖
𝒎 𝟗

13. DESIGN PROCEDURE (continue) For the output x
Code Conversion from BCD to Excess-3 code (continue)
For the output x
𝒎 𝟎
𝒎 𝟏
𝒎 𝟐
𝒎 𝟑
𝒎 𝟒
𝒎 𝟓
𝒎 𝟔
𝒎 𝟕
𝒎 𝟖
𝒎 𝟗

14. Combinational Circuits
DESIGN PROCEDURE (continue)
Code Conversion from BCD to Excess-3 code (continue)
For the output w
𝒎 𝟎
𝒎 𝟏
𝒎 𝟐
𝒎 𝟑
𝒎 𝟒
𝒎 𝟓
𝒎 𝟔
𝒎 𝟕
𝒎 𝟖
𝒎 𝟗

15. DESIGN PROCEDURE (continue)
Code Conversion from BCD to Excess-3 code (continue)
𝑧= 𝐷 ′
𝑦=𝐶𝐷+ 𝐶 ′ 𝐷 ′ =𝐶𝐷+ 𝐶+𝐷 ′
𝑥= 𝐵 ′ 𝐶+ 𝐵 ′ 𝐷+𝐵 𝐶 ′ 𝐷 ′ = 𝐵 ′ 𝐶+𝐷 +𝐵 𝐶 ′ 𝐷 ′
= 𝐵 ′ 𝐶+𝐷 +𝐵(𝐶+𝐷)′
𝑤=𝐴+𝐵𝐶+𝐵𝐷=𝐴+𝐵(𝐶+𝐷)
The OR gate (𝐶+𝐷) has been used to implement partially each of three outputs.

16. DESIGN PROCEDURE (continue)
Adder
Digital computers perform different arithmetic operations. The most basic arithmetic operation is the addition of binary digits.
The simple addition consists of four possible elementary operations: 0+0=0, 0+1=1, 1+0=1, and 1+1=10.
The first three operations produce only one digit. The forth operation produces two digits when both inputs are 1’s.
The higher significant bit of the result is called carry C .
The combinational circuit the performs addition of two bits is called Half adder.
The combinational circuit that performs addition of three bits (two significant bits plus the previous carry Ci) is called Full Adder.
Half Adder x y S C
Full Adder x y S C Ci

17. DESIGN PROCEDURE (continue) Adder (continue) Half adder
The truth table of the half adder is:
The Boolean functions can be obtained directly from the truth table as follows:
𝑺= 𝒙 ′ 𝒚+𝒙 𝒚 ′ =𝒙⊕𝒚
𝑪=𝒙𝒚

18. DESIGN PROCEDURE (continue)
Binary Adder (continue)
Half adder
The implementation of the half adder from the Boolean functions is

19. DESIGN PROCEDURE (continue)
Adder (continue)
Full adder
A full adder is a combinational circuit that performs the arithmetic sum of three bits.
The full adder has three inputs and 2 outputs.
The two bits that to be added are represented by x and y, and z represents the carry from the previous lower significant position.
There are two outputs, the sum S and the carry C.

20. 𝑆=𝑥 ′𝑦 ′ 𝑧+ 𝑥 ′ 𝑦 𝑧 ′ +𝑥 𝑦 ′ 𝑧 ′ +𝑥𝑦𝑧 𝐶=𝑧𝑦+𝑥𝑦+𝑥𝑧
DESIGN PROCEDURE (continue)
Adder (continue)
Full adder (continue)
From the truth table and using maps we can construct the Boolean functions for the outputs.
𝑆=𝑥 ′𝑦 ′ 𝑧+ 𝑥 ′ 𝑦 𝑧 ′ +𝑥 𝑦 ′ 𝑧 ′ +𝑥𝑦𝑧
𝐶=𝑧𝑦+𝑥𝑦+𝑥𝑧 S C

21. The Sum of product implementation of Full Adder is:
DESIGN PROCEDURE (continue)
Binary Adder (continue)
Full adder (continue)
The Sum of product implementation of Full Adder is:
𝑆=𝑥 ′𝑦 ′ 𝑧+ 𝑥 ′ 𝑦 𝑧 ′ +𝑥 𝑦 ′ 𝑧 ′ +𝑥𝑦𝑧
𝐶=𝑧𝑦+𝑥𝑦+𝑥𝑧

22. DESIGN PROCEDURE (continue) Full adder (continue)
Binary Adder (continue)
Full adder (continue)
An alternative implementation of Full Adder can be built using two half adders and OR gate as follows:
𝑆=𝑧⊕ 𝑥⊕𝑦 = 𝑧 ′ 𝑥 ′ 𝑦+𝑥 𝑦 ′ +𝑧 𝑥 ′ 𝑦+𝑥 𝑦 ′ ′
=𝑥 ′𝑦 ′ 𝑧+ 𝑥 ′ 𝑦 𝑧 ′ +𝑥 𝑦 ′ 𝑧 ′ +𝑥𝑦𝑧
𝐶=𝑧𝑦+𝑥𝑦+𝑥𝑧=𝑧𝑦 𝑥 ′ +𝑥 +𝑥𝑦+𝑧𝑥 𝑦 ′ +𝑦
=𝑧𝑦 𝑥 ′ +𝑧𝑦𝑥+𝑧𝑥 𝑦 ′ +𝑧𝑥𝑦+𝑥𝑦=𝑥𝑦 𝑧+1 +𝑧 𝑦 𝑥 ′ +𝑥 𝑦 ′ =𝑥𝑦+𝑧(𝑥⊕𝑦)
Half Adder
Half Adder

23. Thanks