1. Design Methodology Semi Custom ASIC FPGA

2. VLSI Design Methodology Silicon Foundry IC Design Team CAD Tool Provider Design Rules Simulation Models and parameters Mask Layouts Integrated circuits (IC) Process InformationSoftware Tools Relationship between a silicon foundry, an IC design team and a CAD tool provider

5. Top Down (algorithm) Bottom Up (physical)

6. IC Standard ICASSPsASIC Programmable ICSemi Custom ICCustom IC FPGA Gate Array Linear Array Standard Cells Full Custom IC ASSPs : Application Specific Standard Products Application Specific Integrated Circuits (ASICs)

7. ASIC Design Methodologies ASIC Design Methodology  This approach is extremely slow, expensive  It is only used to design very high performance systems Full-custom design  This approach is reasonable fast, less expensive  Most ASICs are currently designed using this method Standard-cell based design  This approach is fast and less expensive  ASIC performance are relatively slow Gate-array based design  The design process is very fast and cost effective  ASIC performance are slow FPGA based design

8. ASIC-Benefit Improve performance Reduce power consumption Mix Analog and Digital Designs Design optimization through IC manufacturing process Development Tools support HDL and Schematic design approach

9. ASIC-Drawbacks Inflexible design Deployed systems can not be upgraded Mistakes in product development are costly Updates requires a redesign Complex and expensive development tools

11. 11 Session Outline (FPGA) Technology/price breakthrough in FPGA devices Why should Windows hardware developers care? Survey of new technologies/vendors Business comparison of FPGA with alternative solutions Advantages/requirements for FPGA development Case Studies Pleora iPort Pinnacle Studio Movie Box Deluxe Summary/Conclusions

12. 12 Technology Breakthrough Impacts Windows-Compatible Hardware Market Field Programmable Gate Arrays (FPGAs) break through price/capability barriers 1 million gates drop from $200+ to <$20 90nm will offer another >2X improvement 32 bit RISC processors “for free” Embedded “soft” 32-bit processors debut allowing complete System- on-Chip designs Previously relegated to high-margin/low-volume applications

13. 13 Why Should We Care? Cost-effective FPGAs Enable New Windows- Compatible Products Greater product differentiation Functionality and performance never available at this price point Shorter development cycles = faster time to market Improved product flexibility = longer market life Reduced part inventory More product variants

14. 14 New Low-Cost Technologies FPGA Families Altera: Cyclone Xilinx: Spartan 3 QuickLogic: QuickMIPS, Eclipse II Actel: ProASIC Plus Embedded Processors Altera: Nios Xilinx: MicroBlaze QuickLogic: MIPS Actel: 8051

15. 15 Three Choices For Windows- Compatible Hardware Development 1. Develop conservative products based on standard chipsets Little differentiation Minimal margin Straight to commodity 2. Develop an ASIC 3. Use new FPGA technologies Let’s compare options 2 and 3…

16. 16 ASIC Versus FPGA Comparison Tooling cost Non-recurring engineering costs (NRE) Time to market Product risk Product flexibility Inventory simplification

17. 17 ASIC Versus FPGA Tools ASIC Requirements Average seat of EDA tools $200K/engineer HDL Simulation, Synthesis, Timing analysis, Test insertion, Place-and route, Formal verification, Floorplanning, DRC… Usually involves multiple EDA vendors FPGA Requirements Average seat $2K-$3K/yr Simulation, Synthesis, Place-and-route Adequate tools provided by FPGA vendors Value-added tools from EDA vendors ~$20-30K

18. 18 Non-Recurring Engineering (NRE) ASIC Designs NRE for ASIC Designs ~$500K/run for.13µ Each subsequent re-spin costs another NRE For new 90nm technology NRE >$1M High-risk methodology requiring massive volume to recoup costs FPGA Designs No NRE charges Some cost-reduction available by ASIC conversion with minimal (<$100K) NRE Cost of FPGA device is offset by NRE in all but the highest volume applications

19. 19 Time To Market ASIC Designs Typical design cycle 12-18 months, minimum 9 months Additional re-spins add 8-10 weeks each FPGA Designs Typical design cycle 4 months Re-spins not an issue

20. 20 Extremely Fast Time-To-Prototype Software-based prototype in days System assembly on FPGA in minutes with processor, memory, bus, interfaces, peripherals C/C++ based application (with RTOS if needed) running in minutes using actual hardware Iterative development/refinement flow Performance-critical routines easily migrated to “hardware” implementations Software development in parallel with working hardware Embedded “virtual instrumentation” offers in-circuit debugging Allows evolutionary design style

21. 21 Benefits Of FPGA-Based Design Improved product flexibility Changes hardware/software up to (and even after) deployment Inventoried parts can be re-deployed in multiple applications More product variants on single platform Upgrade/enhance in the field Reduce inventory Single part for multiple variations and versions of product

22. 22 What’s Needed For FPGA-Based Product Development? Complete toolsets provided by FPGA vendors Robust libraries of pre-tested IP components Processor cores (8,16,32 bit configurable) Peripherals (USB, PCI, I/O, DSP, ethernet, Memory…) Ready-to-use development prototyping boards for a variety of application types Development environments are PC/Windows- based, no UNIX workstations required

23. 23 Case Study: Pleora iPort (~USD500) High-speed video-over-ethernet peripheral with Altera Cyclone FPGA ~10X price/performance improvement over frame-grabber solutions Gigabit ethernet versus expensive video cabling Multiple video sources to single PC, or many-to-many Longer reach

24. 24 Case Study: Pleora iPort FPGA-based frame grabber low-cost, high-speed processing standardized (Ethernet) interfaces Low cost-per-gate at high performance Flexible memory architecture for buffering Drop-in PCI core for interface with Intel Network I/F

25. 25 FPGA Benefits To Pleora Reduced system cost Sub-$20 FPGA is 20% of product cost Dramatically shorter design cycle Multiple product variants with single board Inventory one part and deliver variations based on product mix Enabler – ASIC-based solution not an option at target volumes

26. 26 Pinnacle Studio Movie Box Deluxe (~USD 500) “Without the FPGA option, we probably wouldn’t have pursued the project” - Bernd Riemann, Director Hardware Engineering Pinnacle Systems GmbH Uses Altera Cyclone FPGA for translation between video/audio I/O Development time – 6 mos. with 2 engineers ASIC solution would have added 1 year to development FPGA ~20% of total BOM cost Using FPGA in more and more projects

27. 27 Pinnacle Studio Movie Box Deluxe Remarkable leverage of FPGA reprogrammability 3 FPGAs in 1 Device hardware reconfigures itself based on operating mode Embedded memory sufficient for buffering – no external I/O required Changes made right up to (and after) shipment Hardware design loaded at runtime from Windows drivers Device shipped with no configuration on board User updates possible by downloading new drivers/patches Feature set could be modified with no hardware changes Separate versions possible for NTSC, PAL, etc. Follow-on improvements could be added in future versions Business immunity from hardware design errors (and marketing errors as well)

28. 28 What Applications Benefit From FPGA? Windows-compatible applications that challenge performance barriers… High computational load: Digital Signal Processing (DSP) Video Digital TV Speech recognition High embedded software content Embedded soft-cores offer unprecedented capability

29. 29 What Does The Future Hold? Tomorrow’s “Systems Designer” is today’s “Software Engineer” Example: Nallatech, Ltd. of Scotland Prototyped entire system in C on embedded Xilinx MicroBlaze SW engineer ran project Performance-critical modules moved into hardware (FPGA fabric) New tools rolling out for C-based HW compilation Windows-compatible hardware becomes an extension of SW applications development

30. 30 Summary FPGAs offer significant benefits to PC-based hardware development projects Reduced/more predictable development schedules Earlier prototypes Lower development cost More flexible, upgradeable products with longer market life Greater capability/performance at lower price point Reduced BOM, more flexible inventory Reduced product risk

31. 31 Community Resources Community Sites http://www.microsoft.com/communities/default.mspx List of Newsgroups http://communities2.microsoft.com/communities/newsgroups/en- us/default.aspx http://communities2.microsoft.com/communities/newsgroups/en- us/default.aspx Attend a free chat or webcast http://www.microsoft.com/communities/chats/default.mspx http://www.microsoft.com/seminar/events/webcasts/default.mspx Locate a local user group(s) http://www.microsoft.com/communities/usergroups/default.mspx Non-Microsoft Community Sites http://www.microsoft.com/communities/related/default.mspx