1. ECE 551: Digital System Design & Synthesis Motivation and Introduction Lectures Set 1 (3 Lectures)

2. 1/22/20162 Overview Course Introduction Overview of Contemporary Digital Design –LayoutLayout –Application Specific Integrated Circuit (ASIC) TechnologiesApplication Specific Integrated Circuit (ASIC) Technologies –IC CostsIC Costs –ASIC Design FlowsASIC Design Flows –The Role of HDLs and SynthesisThe Role of HDLs and Synthesis Summary

3. 1/22/20163 Course Introduction Purpose: –To provide knowledge and experience in performing contemporary logic design based on 1) hardware description languages (HDLs), 2) HDL simulation, 3) automated logic synthesis and 4) timing analysis with consideration for a) pragmatic design and test issues, b) chip layout issues, and c) design reuse in the context of the ASIC (Application Specific Integrated Circuit) and SOC (System-On-a-Chip) technologies. Conduct and Outline –Go through the course homepage for 551 –http://www.cae.wisc.edu/~ece551/spring02/general/con duct.htmlhttp://www.cae.wisc.edu/~ece551/spring02/general/con duct.html

4. 1/22/20164 Layout IC are produced from masks that correspond to geometric layouts produced by the designer or automatically. In CMOS, a typical IC cross-section: Substrate Oxide Transistor Metal 3 Metal 2 Metal 1 Polysilicon Diffusion Channel

5. 1/22/20165 Layout (continued) The layout corresponding to the cross-section: –The transistor is outlined in broad yellow lines. –Everything else is interconnect. Channel Transistor

6. 1/22/20166 IC Implementation Technologies Implementation technologies are distinguished by: –The levels of the layout 1) transistors and 2) interconnect that are: Common to distinct IC designs (L1) Different for distinct IC designs (L2) –The use of predesigned layout cells Predesigned cells are used (P1) Predesigned cells are not used (P2) –Mechanism used for instantiating distinct IC designs: Metallization (M) Fuses or Antifuses (F) Stored Charge (C) Static Storage (R)

7. 1/22/20167 IC Implementation Technologies (continued) STANDARD IC FULL CUSTOM SEMI - CUSTOM FIELD PROGRAMMABLE STANDARD CELL GATE ARRAY, SEA OF GATES ASICFPGAPLD

8. 1/22/20168 IC Implementation Technologies (continued) Technologies in terms of Distinguishing Features: –Full Custom – P2, M Transistors – L2, Interconnects – L2 –Standard Cell – P1, M Transistors – L2, Interconnects – L2 –Gate Array, Sea of Gates – P1, M Transistors – L1, Interconnects – L2 –FPGA – P1, F or R Transistors – L1, Interconnects – L1 –PLD – P1, F or C Transistors – L1, Interconnects – L1

9. 1/22/20169 IC Implementation Technologies (continued) Technologies in terms of shared fabrication steps (can be used for common transistors/interconnects): –Full Custom and Standard Cells – all layers are custom fabricated –Gate Arrays and Sea of Gates – only interconnect (metallization) layers custom fabricated –FPGAs and PLDs – nothing is custom fabricated Consequences due to economy-of-scale: –Fab costs reduced for Gate Arrays and Sea of Gates –Fab costs further reduced for FPGAs and PLDs

10. 1/22/201610 IC Implementation Technologies (continued) Technologies in terms of layout styles: Adjustable Spacing Megacells Standard Cell Gate Array - Channeled … … Fixed Spacing Base Cell

11. 1/22/201611 IC Implementation Technologies (continued) Technologies in terms of layout styles: … Base Cell Gate Array - Channel-less (Sea of Gates) Gate Array - Structured … … Fixed Embedded Block

12. 1/22/201612 IC Costs An example: 10,000 gate circuit [1] –Fixed costs Standard Cell - $146,000 Gate Array - $86,000 FPGA - $21,800 –Variable costs Standard Cell - $8 per IC Gate Array - $10 per IC FPGA - $39 per IC

13. 1/22/201613 IC Costs (continued) An example: 10,000 gate circuit

14. 1/22/201614 IC Costs (continued) Why isn’t FPGA cheaper per unit due to economy-of-scale? –The chip area required by each of the successive technologies from Full Custom to FPGAs increases for a fixed-sized design. –The larger the chip area, the poorer the yield of working chips during fabrication –Also, due to increased sales, FPGA prices have declined since the mid-90’s much faster than the other technologies.

15. 1/22/201615 CELLS Can of different sizes, shapes and functions varying from transistors, on-chip resistors to large memory arrays or even a processor (often referred to as IP “intellectual property” core) Typically cells in todays cell libraries are: –Gates – AND, OR, NAND, NOR, NOT –Complex gates – AOI, OAI –Storage elements – Flip-Flops, Lateches

16. 1/22/201616 ASIC Cell Libraries Sources – –ASIC vendor use tools supplied by the vendor, often details are not provided (proprietary) –Third party Details are provided, often general enough to be used with a known technology, testing may not be necessary –Build your own Complete the layout and test to verify the design and performance, often complex and expensive

17. 1/22/201617 ASIC Cell Libraries (contd.) Cells –Transistors and transistors as resisitors –Combinational logic cells Gates – number of inputs, performance (drive capability and width) Complex gates –Sequential cells Flip-flops, latches –Datapath logic cells Multiplexors, adders, ALU, mutipliers

18. 1/22/201618 Draw Datapath Schematics * Traditional ASIC Design Flow Write Specifications Define System Architecture Partition - Data- path &Control Define State Diag/Tables Draw Control Schematics * Integrate Design* Do Physical Design* Implement* * Steps followed by validation and refinement

19. 1/22/201619 Traditional Flow Problems Schematic Diagrams –Limited descriptive power State Diagrams and Algorithmic State Machines –Limited portability –Limited complexity –Difficult to describe parallelism –Limited complexity  Tedious and/or Repetitive Detail

20. 1/22/201620 How about HDLs Instead of Diagrams? HDLs –Highly portable (text) –Describes multiple levels of abstraction –Represents parallelism –Provides many descriptive styles Structural Register Transfer Level (RTL) Behavioral –Serve as input for synthesis

21. 1/22/201621 How about Synthesis instead of Manual Design? Increased design efficiency Reduces verification/validation problem Ability to explore more of overall design space Are there disadvantages? Potential for better optimization

22. 1/22/201622 Refine to RTL (HDL)* Physical Design* Synthesis Design Flow Write Specifications Define Architec- ture (HDL)* Implement* * Steps followed by validation and refinement Partition Arch- itecture Synthesize RTL*

23. 1/22/201623 Synthesize RTL* Contemporary Design Flow Write Specifications Define Architec- ture (HDL)* Implement* * Steps followed by validation and refinement Partition Arch- itecture Refine to RTL* Preliminary Physical Design Select IP Cores Physical Design*

24. 1/22/201624 Newer technologies and design flows System on Chip (SOC) –Designers are provided with IP cores –The main function is to glue many cores and generate/design only those components for which cores and designs may not be available –Used in ASIC as well as custom design environment –The issues relevant to this will be discussed near the end of the course

25. 1/22/201625 Summary –Course Conduct – Be familiar with it –Application Specific Integrated Circuit (ASIC) Technologies – provides a basis for understanding what we are designing –IC Costs – Gives a basis for technology selection –ASIC Design Flows The role of HDLs and synthesis Provides a structure for what we are to learn

26. 1/22/201626 References 1)Smith, Michael J. S., Application-Specific Integrated Circuits, Addison-Wesley, 1997. 2)For layout refer to texts for ECE 555 and ECE 755