1. EKT 221 / 4 DIGITAL ELECTRONICS II
Chapter reVieW
Sequential Logic Circuit

2. Introduction to Sequential Circuits
Inputs
Outputs
Combina-tional
Logic
A Sequential circuit contains:
Storage elements: Latches or Flip-Flops
Combinatorial Logic:
Implements a multiple-output switching function
Inputs are signals from the outside.
Outputs are signals to the outside.
Other inputs, State or Present State, are signals from storage elements.
The remaining outputs, Next State are inputs to storage elements.
Storage Elements
State
Next
State

3. Introduction to Sequential Circuits
Inputs
Outputs
Combina-tional
Logic
Combinatorial Logic
Next state function Next State = f(Inputs, State)
Output function (Mealy) Outputs = g(Inputs, State)
Output function (Moore) Outputs = h(State)
Output function type depends on specification and affects the design significantly
Storage Elements
State
Next
State

4. Types of Sequential Circuits
Depends on the times at which:
storage elements observe their inputs, and
storage elements change their state
Synchronous
Behavior defined from knowledge of its signals at discrete instances of time
Storage elements observe inputs and can change state only in relation to a timing signal (clock pulses from a clock)
Asynchronous
Behavior defined from knowledge of inputs an any instant of time and the order in continuous time in which inputs change
If clock just regarded as another input, all circuits are asynchronous!
Nevertheless, the synchronous abstraction makes complex designs tractable!

5. 3.1 Flip-flop & Register ~ Latches ~ Edge-triggered flip-flops
~ Master-slave flip-flops
~ Flip-flop operating characteristics
~ Flip-flop applications
~ One-shots
~ The 555 timer

6. Introduction
Latches and flip-flops are the basic single-bit memory elements used to build sequential circuit with one or two inputs/outputs, designed using individual logic gates and feedback loops.

7. Introduction Latches:
The output of a latch depends on its current inputs and on its previous output and its change of state can happen at any time when its inputs change.
Flip-Flops:
The output of a flip-flop also depends on current inputs and its previous output but the change of state occurs at specific times determined by a clock input.

8. Introduction Latches: S-R Latch Gated S-R Latch Gated D-Latch
Flip-Flops:
Edge-Triggered Flip-Flop (S-R, J-K, D)
Asynchronous Inputs
Master-Slave Flip-Flop
Flip-Flop Operating Characteristics
Flip-Flop Applications
One-shots & The 555 Timer

9. Latches
Type of temporary storage device that has two stable (bi-stable) states
Similar to flip-flop – the outputs are connected back to opposite inputs
Main difference from flip-flop is the method used for changing their state
S-R latch, Gated/Enabled S-R latch and Gated D latch

10. S-R (SET-RESET) Latch
Active-HIGH input S-R Latch Active-LOW input S-R Latch

11. Logic symbols for the S-R and S-R latch

12. Negative-OR equivalent of the NAND gate S-R latch

14. Truth table for an active-LOW input S-R latch

15. Assume that Q is initially LOW1 2 3 4 5 6 7
Waveforms

16. Gated S-R Latch
A gate input is added to the S-R latch to make
the latch synchronous.
In order for the set and reset inputs to change
the latch, the gate input must be active
(high/Enable).
When the gate input is low, the latch remains in
the hold condition.

17. A gated S-R latch

18. Gated S-R latch waveform:1 2 3 4 5

19. Truth Table for Gated S-R Latch
S R G Q Q’
Q Q’ Hold
Q Q’ Hold
Q Q’ Hold
Q Q’ hold
Q Q’ hold
set
reset
not allowed

20. Gated D Latch (74LS75)
The D (data) latch has a single input that is used to set and to
reset the flip-flop.
When the gate is high, the Q output will follow the D input.
When the gate is low, the Q output will hold.

21. Gated S-R Latch Q output waveform if the inputs are as shown:
The output follows the input when the gate is high but is in a hold
when the gate is low.

22. Gated D Latch (74LS75)

23. Edge-triggered Flip-flop Logic Positive edge triggered and Negative edge-triggered
All the above flip-flops have the triggering input called clock (CLK/C)

24. Clock Signals & Synchronous Sequential Circuits
Rising edges of the clock
(Positive-edge triggered)
Falling edges
of the clock
(Negative-edge triggered)
Clock signal
Clock Cycle
Time 1
A clock signal is a periodic square wave that indefinitely switches values from 0 to 1 and 1 to 0 at fixed intervals.

25. Operation of a positive edge-triggered S-R flip-flop
is invalid or not allowed

26. Example:

27. A positive edge-triggered D flip-flop formed with an S-R flip-flop and an inverter.
D CLK/C Q Q’_________________
↑ 1 0 SET (stores a 1)
↑ RESET (stores a 0)

28. Example:

29. Truth Table for J-K Flip Flop
J K CLK Q Q’
0 0 Q0 Q0’ Hold
Reset
Set
1 1 Q0’ Q0 Toggle (opposite state)

30. Transitions illustrating the toggle operation when J =1 and K = 1.

31. Edge-triggered J-K flip-flop
The edge-triggered J-K will only accept the J and K
inputs during the active edge of the clock.
The small triangle on the clock input indicates that the
device is edge-triggered.
A bubble on the clock input indicates that the device
responds to the negative edge. no bubble would indicate
a positive edge-triggered device.

32. A simplified logic diagram for a positive edge-triggered J-K flip-flop.

33. Example: Positive edge-triggered

34. Example: Negative edge-trigerred

35. Logic symbol for a J-K flip-flop with active-LOW preset and clear inputs.

36. Example:

37. Edge-triggered flip-flop logic symbols (cont’d)
The J-K flip-flop has a toggle mode of operation when both
J and K inputs are high.Toggle means that the Q output
will change states on each active clock edge.
J, K and Cp are all synchronous inputs.
The master-slave flip-flop is constructed with two latches.
The master latch is loaded with the condition of the J-K inputs while
the clock is high. When the clock goes low, the slave takes on the
state of the master and the master is latched.
The master-slave is a level-triggered device.
The master-slave can interpret unwanted signals on the J-K inputs.

38. Basic logic diagram for a master-slave J-K flip-flop.

39. Pulse-triggered (master-slave) J-K flip-flop logic symbols.

40. Truth Table for Master-Slave J-K Flip Flop
J K CLK Q Q’
0 0 Q0 Q0’ Hold
Reset
Set
1 1 Q0’ Q0 Toggle (opposite state)

41. Flip-Flop Applications
Parallel Data Storage
Frequency Division
Counting

42. Flip-flops used in a basic register for parallel data storage.

43. J-K flip-flop as a divide-by-2 device
J-K flip-flop as a divide-by-2 device. Q is one-half the frequency of CLK.

44. Two J-K flip-flops used to divide the clock frequency by 4
Two J-K flip-flops used to divide the clock frequency by 4. QA is one-half and QB is one-fourth the frequency of CLK.

45. Flip-flops used to generate a binary count sequence
Flip-flops used to generate a binary count sequence. Two repetitions (00, 01, 10, 11) are shown.

46. Flip-Flop Operating Characteristics
Propagation Delay Times
Set-up Time
Hold Time
Maximum Clock Frequency
Pulse Width
Power Dissipation

47. Comparison of operating parameters for 4 IC families of flip-flop of the same type

48. There are several other parameters that will also be listed in a manufacturers data sheet.
Maximum frequency (Fmax) - The maximum frequency allowed at the clock input.
Clock pulse width (LOW) [tW(L)] - The minimum width that is allowed at the clock input during the LOW level.
Clock pulse width (HIGH) [tW(H)] - The minimum width that is allowed at the clock input during the high level.
Set or Reset pulse width (LOW) [tw(L)] - The minimum width of the LOW pulse at the set or reset inputs.

49. Basic operation of a 555 Timer
Threshold
Control Voltage
Trigger
Discharge
Reset
Output

50. Functional Diagram of 555 Timer

51. 555 Timer as a one shot
tw = 1.1R1C1 = 1.1(2000)(1F) = 2.2ms

52. Astable operation of 555 Timer
tH = .7 (R1+R2)C1 =2.1ms tL = .7R2C1 = 0.7ms

53. Topics
4-1. Sequential Circuit Definitions.
4-2. Latches
4-3. Flip-flops.

54. Block Diagram of a Sequential Circuit

55. Logic Structures for Storing Information

56. Synchronous Clocked Sequential Circuit

57. Latch A type of temporary storage device.
Similar to FFs because they are both bistable devices, by means of a feedback arrangement.
The main difference is the method used for changing their state.

58. Types of Latches S-R (Set-Reset) Latch S-R Latch
S-R Latch with control input
D Latch
Sketch the back box views for each latch..

59. SR Latch with NOR Gates

60. Logic Simulation of SR latch Behavior

61. SR Latch with NAND gates

62. SR Latch with Control Input

63. D Latch

64. Edge-Triggered Flip-flops
Flip-flops are synchronous bistabe devices.
Synchronous: because the output changes state ony at a certain point on a triggering input, i.e. CLK, which is the control input.
Edge-triggered flip-flop: changes state at either the positive edge (rising edge) or at the negative edge (falling edge) of the cock pulse.

65. Types of Flip-fops Edge-Triggered Master-Slave Any more? S-R flip-flop
D flip-flop
J-K flip-flop
Master-Slave
Any more?
Sketch the back box views for each
flip-flop...

66. D-Type Positive-Edge-Triggered Flip-Flop

67. Positive Edge-Triggered JK Flip-Flop

68. Master-Slave Flip-flop
Is pulse-triggered.
Data is entered into the flip-flop at the leading edge of the cock pulses, but the output is only reflected at the trailing edge.
Does not allow data to change while the clock pulse is still active.

69. Master-Slave SR Flip-Flop

70. Logic Simulation of a master-Slave Flip-Flop

71. Master-Slave JK Flip-Flop

72. Standard Graphic Symbols for Latch and Flip-Flops

73. Flip-Flop Characteristic Table

74. 4-4 Sequential Circuit Analysis
Behaviour of a sequential circuit, is determined by:
The inputs.
The outputs.
The Present state.
Flip-flops – can be any type, Logic diagram – may or may not be included.

75. Input equations Flip-flop input equation JA and KA : Boolean variables
JA = ( XB +NY.C )
KA = ( Y.NB + C )
JA and KA : Boolean variables
J and K – inputs of a JK flip-flop.
Subscript A – name of flip-flop output.
C – clock input.
X, B and Y – inputs to combinational circuit.

76. Implementing Input Equations

77. Another Example of a Sequential Circuit
DA = (AX +BX) Equations for FF inputs
DB = NA.X
Y = ( A+B ) . NX - Equation for output Y
Subscripts A and B – names of FF outputs.

78. Another Example of a Sequential Circuit

79. State table for Circuit of Fig 4.18

80. Two-Dimensional State Table for the Circuit in Figure 4.18

81. Logic Diagram and State Table for DA

82. State Table for Circuit with JK Flip-Flops

83. State Diagram

84. Fig 4.21 Construction of a State Diagram

85. Table 4.5 State Table for State Diagram in Fig 4.21

86. Sequence Tables for Code Converter Example

87. Construction of a State Diagram

88. Table 4.5 with names Replaced by Binary Codes

89. State Table for Design Example

90. State Diagram for Design Example

91. Maps for Input Equations and Output Y

92. Logic Diagram for Sequential Circuit with D Flip-Flops

93. State table for Second Design Example

94. Maps for Simplifying Input Equations

95. Design Using D Flip-flops

96. Flip-Flop Characteristic Table

97. Flip-Flop Excitation Tables

98. Design Procedure using JK Flip-Flops

99. Maps for J and K Input Equations

100. Fig 4.28 Logic Diagram for Sequential Circuit with JK Flip-flops

101. Logic Simulation Verification for the Circuit in Fig 4.28

102. In-class Exercise … Referring to Fig. 4-29. Photostate Fig. 4-29.
Draw guide lines for each positive clock edge, and:
Identify the input values.
Obtain the output values.
Produce a table to list your answers in (i) and (ii). Verify these values with Table 4-11.

103. … In-class Exercise 2. Using the State Table as in Table 4-11,
Produce 2 new columns, TA and TB.
Obtain the T-FF input equations for A and B.
Draw the logic diagram for this sequential circuit using T-FFs.

104. More Assignment
Chapter 4
24, 30, 31, 33

105. State Diagrams
The sequential circuit function can be represented in graphical form as a state diagram with the following components:
A circle with the state name in it for each state
A directed arc from the Present State to the Next State for each state transition
A label on each directed arc with the Input values which causes the state transition, and
A label:
On each circle with the output value produced, or
On each directed arc with the output value produced.

106. State Diagrams Label form: On circle with output included:
state/output
Moore type output depends only on state
On directed arc with the output included:
input/output
Mealy type output depends on state and input

107. Example 1: State Diagram
A B
0 0
0 1
1 1
1 0
x=0/y=1
x=1/y=0
x=0/y=0
Which type?
Diagram gets confusing for large circuits
For small circuits, usually easier to understand than the state table
Type: Mealy

108. Moore and Mealy Models
Sequential Circuits or Sequential Machines are also called Finite State Machines (FSMs). Two formal models exist:
In contemporary design, models are sometimes mixed Moore and Mealy
Moore Model
Named after E.F. Moore.
Outputs are a function ONLY of states
Usually specified on the states.
Mealy Model
Named after G. Mealy
Outputs are a function of inputs AND states
Usually specified on the state transition arcs.

109. Moore and Mealy Example Diagrams
Mealy Model State Diagram maps inputs and state to outputs
Moore Model State Diagram maps states to outputs 1
x=1/y=1
x=1/y=0
x=0/y=0
1/0
2/1
x=1
x=0
0/0

110. Moore and Mealy Example Tables
Mealy Model state table maps inputs and state to outputs
Moore Model state table maps state to outputs
Present
State
Next State
x=0 x=1
Output 1
Present
State
Next State
x=0 x=1
Output 1 2