1. Norhayati Soin 05 KEEE 4425 WEEK 7/1 23/8/2005 LECTURE 9: KEEE 4425 WEEK 7 CMOS LAYOUT AND STICK DIAGRAM (Cont’d)

2. Norhayati Soin 05 KEEE 4425 WEEK 7/1 23/8/2005 CMOS layers - representing the design The design of integrated circuits in silicon is a process of turning a specification into mask layouts for processing the silicon. In design we need a simple way of representing layer and topology so that we can do initial design work with relatively simple diagrams if we so desire. A simple expedient in this respect is the use of stick diagram. In stick diagram : wires become thin lines contacts become small boxes colours remain unchanged

3. Norhayati Soin 05 KEEE 4425 WEEK 7/1 23/8/2005 CMOS layers - representing the design Translation of stick diagram (left) into mask layouts (right). 2.

4. Norhayati Soin 05 KEEE 4425 WEEK 7/1 23/8/2005 CMOS Joining Rules 1 2 1 2 2 1 2 3 3 n-type diffusion √ p-type diffusion poly Metal 1Metal 2 n-type diffusion x x p-type diffusion x √ x Poly √ x Metal 1 √ Metal 2 x x x √ 2 2 1

5. Norhayati Soin 05 KEEE 4425 WEEK 7/1 23/8/2005 CMOS Joining Rules 1 2 3 Symbolkey √ allowed - connection formed x prohibited transistor formed contact needed if connection required, otherwise no connection is made via needed if connection required, otherwise no connection is made

6. Norhayati Soin 05 KEEE 4425 WEEK 7/1 23/8/2005 Ndiff and Pdiff The Ndiff layer ( ) is formed from silicon that has impurities added to it. This causes it to be negatively diffused (or doped), and ends up rich in electrons. Therefore Ndiff is negatively charged. With Pdiff ( ) the reverse happens silicon is implanted with positive charges (or is positively doped) so that is rich in holes. Hence the layers is positively charged. There are two methods for achieving this: Diffusion: the silicon surface is exposed selectively to the impurities in a gaseous form and they simply diffuse into the wafer. Implantation: the impurities are accelerated electromagnetically and "shot" into the exposed surface of the wafer. It is these properties of Ndiff and Pdiff allow them to be connected with other layers to form transistors.

7. Norhayati Soin 05 KEEE 4425 WEEK 7/1 23/8/2005 Transistor Structures VLSI layout design consist of creating appropriate masks that define the sizes and location of components and the necessary interconnections. To facilitate design and checking different colours are used for each separate mask required. Polysilicon crossing a diffused area creates a transistor switch; wherever red cross green an an n-transistors is formed and p-transistor is formed wherever red cross yellow Transistor has three terminals: a and b called source and drain, and c called gate.

8. Norhayati Soin 05 KEEE 4425 WEEK 7/1 23/8/2005 NMOS transistor The n-type transistor is an active-high switching device which conducts and acts as a closed when its gate voltage is HIGH.HIGH The absence of a bubble at the gate of the of NMOS device means it conducts when its gate is at high potential. Unfortunately, this switch is not good at all voltages, the n-transistor switch is only good at passing logic "0"; the logic "1" is passed badly (voltage is reduced).

9. Norhayati Soin 05 KEEE 4425 WEEK 7/1 23/8/2005 PMOS transistor The p-type transistor is an active-low switching device that conducts when its gate voltage is LOW. This is shown by the circuit symbols.LOW The "bubble" at the gate of the PMOS transistor means that its gate must be at a low voltage in order for it to turn on. The p-transistor is only good at passing "1".

10. Norhayati Soin 05 KEEE 4425 WEEK 7/1 23/8/2005 Question 1. The diagram below shows two horizontal "wires" crossing five vertical ones. Which of the resultant 10 junctions is legal CMOS and what is formed there? Express your result in a tabular form.

11. Norhayati Soin 05 KEEE 4425 WEEK 7/1 23/8/2005 Solution Question 1. polymetal p-type diffusion n-type diffusion metal p-type diffusion (2) (1) poly (3) (4) Notes: Note that P-DIFF to METAL junctions are permitted but need a contact. In the question, none exist at (1) so the two layers are isolated. A contact is present at (2) so the two layers are electrically connected. The POLY to METAL junction is permitted but requires a contact. There is none at (3) so the layers are isolated. Compare this with (4) where there is a contact.

12. Norhayati Soin 05 KEEE 4425 WEEK 7/1 23/8/2005 Solution symbolkey allowed - connection formed prohibited transistor formed contact needed if connection required, otherwise no connection is made

13. Norhayati Soin 05 KEEE 4425 WEEK 7/1 23/8/2005 Designing the inverter: Step 1 Starting from the circuit diagram of inverter, we can design the stick layout step by step. Two horizontal wires are used for connection with VSS and VDD. This is done in metal2, but you can decide to use metal 1instead.

14. Norhayati Soin 05 KEEE 4425 WEEK 7/1 23/8/2005 Designing the inverter: Step 2 Two vertical wires (pdiff and ndiff) are used to represent the p-transistor (yellow) and n-transistor (green).

15. Norhayati Soin 05 KEEE 4425 WEEK 7/1 23/8/2005 Designing the inverter: Step 3 Then the gates of the transistors are joined with a polysilicon wire, and connected to the input.

16. Norhayati Soin 05 KEEE 4425 WEEK 7/1 23/8/2005 Designing the inverter: Step 4 The drains of two transistor are then connected with metal1 and joined to the output. There cannot be direct connection from n-transistor to p- transistors.metal1

17. Norhayati Soin 05 KEEE 4425 WEEK 7/1 23/8/2005 Designing the inverter: Step 5 The sources of the transistors are next connected to VSS and VDD with metal1. Notice that vias are used, not contacts.

18. Norhayati Soin 05 KEEE 4425 WEEK 7/1 23/8/2005 Alternative inverter stick diagram Here we have alternative inverter stick diagram (metal1 is used instead of metal2 to connect VSS and VDD supply)... and corresponding mask layout.

19. Norhayati Soin 05 KEEE 4425 WEEK 7/1 23/8/2005 Contacts Layers of metal, polysilicon, and diffused material are normally isolated by silicon dioxide. After the masks for a layout are designed a scheme for interconnecting appropriate layers is required, and masks are needed to define areas where the oxide is to be etched to produce the desired contacts. Metal is normally connected to either polysilicon or diffusion by a contact cut. Cuts called vias are used to make contact between two metal layers. First-level metal is usually used to make contact to polysilicon or diffusion, and connections between second-level metal and poly or diffusion areas is normally done by connection the second metal to the first layer, which in turn connects to the diffusion and polysilicon. Plan view

20. Norhayati Soin 05 KEEE 4425 WEEK 7/1 23/8/2005 Contacts Plan view Cross-section view

21. Norhayati Soin 05 KEEE 4425 WEEK 7/1 23/8/2005 Contacts Contact cut Via cut Metal 1 Metal 2 Gate oxide Field Oxide Polysilicon N-Diffusion P-Diffusion

22. Norhayati Soin 05 KEEE 4425 WEEK 7/1 23/8/2005 NAND Gate 2 i/p NAND - vertical transistors

23. Norhayati Soin 05 KEEE 4425 WEEK 7/1 23/8/2005 NAND Gate 2 i/p NAND - vertical transistors

24. Norhayati Soin 05 KEEE 4425 WEEK 7/1 23/8/2005 3 i/p NAND gate stick diagrams

25. Norhayati Soin 05 KEEE 4425 WEEK 7/1 23/8/2005 Example 1 Sketch a stick diagram for a 4-input NOR

26. Norhayati Soin 05 KEEE 4425 WEEK 7/1 23/8/2005 Example 1: solution

27. Norhayati Soin 05 KEEE 4425 WEEK 7/1 23/8/2005 Example 2