1. © 2003 Xilinx, Inc. All Rights Reserved Answers DSP Design Flow

2. Answers - 10 - 3 © 2003 Xilinx, Inc. All Rights Reserved Lab 1: Wrap up Implementation results: 66 Slices, ~130 MHz Important to notice: –Global clock buffer is automatically instantiated –Embedded multiplier is used by default in Virtex™-IIP devices. In this lab, the option was turned off in order to use slice-based multipliers Timing constraint should always be used to achieve the performance required –XCF file must be generated manually Remember size to compare with the other flows

3. Answers - 10 - 4 © 2003 Xilinx, Inc. All Rights Reserved Lab 2: Wrap up Implementation results: 71 slices, 175 MHz Important to notice: –Global clock buffer should be instantiated because the synthesis tool may not know which signal is the clock because it is looking at a black box

4. Answers - 10 - 5 © 2003 Xilinx, Inc. All Rights Reserved Module 2: Answers Define the format of the following twos complement binary fraction and calculate the value it represents What format should be used to represent a signal that has: Fill in the table: Using the technique shown, convert the following fractional values… 110001101011 Format = Value = -917 = -28.65625 32 Format = a) Max value: +1 Min value: -1 Quantized to 12 bit data b) Max value: 0.8 Min value: 0.2 Quantized to 10 bit data c) Max value: 278 Min value: -138 Quantized to 11 bit data

5. Answers - 10 - 6 © 2003 Xilinx, Inc. All Rights Reserved Lab 3: Solution MAC using embedded multiplier Slice Count: 24 Slices, 1 embedded multiplier Performance: ~244 MHz (2vp4 -7) MAC using slice-based multiplier Slice Count: 69 Slices Performance: ~182 MHz (2vp4 -7) Multiplier Latency - 2

6. Answers - 10 - 7 © 2003 Xilinx, Inc. All Rights Reserved Module 3: Answers How many clock cycles per input are required for a fully parallel 12-bit data, 20 tap symmetric filter? –Hardware over-sampling rate = 1 The requirement for a filter is to run at 25 MSPS. A 100 MHz system clock is available on the board. What should the hardware over-sampling rate parameter be set to for 8-bit data? –Hardware over-sampling rate = 100/25 = 4 How many clock cycles per input are necessary to process in serial an 11-bit data, 31 tap symmetric filter? –Hardware over-sampling rate = 11 + 1 = 12

7. Answers - 10 - 8 © 2003 Xilinx, Inc. All Rights Reserved Lab 4: Solution 365 slices Clock rate: 229 MHz Sample rate: 229/9 = 25.4 MSPS

8. Answers - 10 - 9 © 2003 Xilinx, Inc. All Rights Reserved Lab 5: Solution Slices: 170 Clock Speed: ~211 MHz

9. Answers - 10 - 10 © 2003 Xilinx, Inc. All Rights Reserved Lab 6: Solution RTL View for Rounding RTL View for Saturation and Rounding

10. Answers - 10 - 11 © 2003 Xilinx, Inc. All Rights Reserved Module 5: What Values Do You Expect? Signed Data Truncate and Wrap Signed Data Output Binary point of 3 Total Number of Bits 3 Bottom of Slice offset by 5 from the LSB Number Input Convert Reinterpret Slice

11. Answers - 10 - 12 © 2003 Xilinx, Inc. All Rights Reserved Lab 7: Blocks-Based Solution Post-Map Resource Estimates – Slices – 15 – FFs – 16 – LUTs – 28

12. Answers - 10 - 13 © 2003 Xilinx, Inc. All Rights Reserved Control Logic Waveform

13. Answers - 10 - 14 © 2003 Xilinx, Inc. All Rights Reserved Lab 7: MCode-Based Solution Post-Map Resource Estimates – Slices – 16 – FFs – 16 – LUTs – 28 function done = term_cnt(count) if count == 183 done = true; else done = false; end

14. Answers - 10 - 15 © 2003 Xilinx, Inc. All Rights Reserved 44.1 kHz 48 kHz 441 kHz CD format DAT format 7056 kHz Sample Period (GCD) Sample Period Gateway InBlockantiAliasFIRantiAliasFIR1Gateway Out Simulink System Sample Period: Module 7 Exercise: Audio Application Analyze the following sampling rate change system that is commonly found in audio broadcasting studios. Determine the Simulink System Sample period: 1/44100 1/4410001/70560001/48000 160/705600016/70560001/7056000147/7056000 1/7056000

15. Answers - 10 - 16 © 2003 Xilinx, Inc. All Rights Reserved CE DQ CE2 D CE3 Q CE X y CE CK CE CE2 CE3 System CLK System CE Sample Rate Control Logic Answer: Audio Application 2 1 3 CE2 CE3 DAT format DAB format 32 kHz 96 kHz 48 kHz Normalized Sample Times:

16. Answers - 10 - 17 © 2003 Xilinx, Inc. All Rights Reserved Answer: Audio Application

17. Answers - 10 - 18 © 2003 Xilinx, Inc. All Rights Reserved Q.What would happen if a full precision adder is used in this example? An error will occur as an infinite loop will be created Module 7: Propagation in Loops

18. Answers - 10 - 19 © 2003 Xilinx, Inc. All Rights Reserved Lab 8: Solution Slice Count: (with MULT18x18) 89 slices Performance ~204 MHz Slice Count: (Slice-based MULT) 126 slices Performance ~ 208 MHz

19. Answers - 10 - 20 © 2003 Xilinx, Inc. All Rights Reserved Lab 9: Solution

20. Answers - 10 - 21 © 2003 Xilinx, Inc. All Rights Reserved Lab 10: Solution