1. L 05 29Jan021 EE 4345 - Semiconductor Electronics Design Project Spring 2002 - Lecture 05 Professor Ronald L. Carter ronc@uta.edu http://www.uta.edu/ronc/

2. L 05 29Jan022 RFP for TP1.1 - TP 1.10 Each of the groups in EE 4345 designated by group leaders will present a proposal for doing a Technology Presentation in TP1.1 - TP1.10 as in assignments Group Leaders –Fares Alnajjar –Jepsy Colon –Robert Colville –Eyad Fanous –Carlos Garcia –Derek Johnson –Nam Nguyen –Peter Presby –Viet Tran –Preeti Yadav

3. L 05 29Jan023 Dates for Technology Project Reports 12 Feb - TP1.1 Text Chapter 2 - 2.1 to 2.4 12 Feb - TP1.2 Text Chapter 2 - 2.5 through 2.7 14 Feb - TP1.3 Text Chapter 3 - Ch 3 - 3.1 14 Feb - TP1.4 Text Chapter 3 - 3.2 19 Feb - TP1.5 Text Chapter 3 - 3.3 19 Feb - TP1.6 Text Chapter 4 - Ch 4 - 4.1 - 4.3.1 21 Feb - TP1.7 Chapter 4-4.3.2(except CMOS and BiCMOS) through 4.4.2 21 Feb - TP1.8 Chapter 5 - Ch 5 - 5.1 through 5.4 26 Feb - TP1.9 Chapter 5 - 5.5 through 5.6 26 Feb - TP1.10 Chapter 6 - Ch 6 (all)

4. L 05 29Jan024 Minimum presentation requirements 25 to 35 minutes. using visuals such as black on white line drawing transparencies which are easily readable from all parts of the classroom, and can be downloaded so that all students can make their own copy. electronic copy as *.doc or *.ppt file of visuals mailed to ronc@uta.edu by noon the day before presentation.

5. L 05 29Jan025 TO RESPOND TO THIS RFP By 5 pm 31 January, each Group Leader will return the following from their group: –A list of all TEN TP numbers, TP1.1 through TP1.10, in rank order of –the preference of the group for presentation. Give the TP number MOST preferred FIRST.

6. L 05 29Jan026 TO RESPOND TO THIS RFP –The Group's plan for making the presentation awarded. Include: a description of the media to be used (transparencies, etc.), extra sources for information presented (other books, etc.), plan for development and presentation of the presentation, and other plans which you believe should warrant awarding your highest preferences.

7. L 05 29Jan027 TO RESPOND TO THIS RFP how each group member will participate in the preparation and presentation of the Technology Presentation - state the specific responsibilities of each member. The TP assignments for TP1.1 through TP1.10 will be announced by 5 PM on 1 February.

8. L 05 29Jan028 Getting started To set up your unix environment follow these steps: Make directory called cadence. Open console and type ftp gamma at login prompt : cxs4776 password: cxs2011 get.cshrc.oo get.cshrc.ic get.simrc get.cdsinit bye

9. L 05 29Jan029 Adding the technology files. Open the console and at prompt type: telnet gamma cxs4776 password: cxs2011 cp –r cadence/ temp exit cp –r /tmp/cadence Take care of the spaces in the commands.

10. L 05 29Jan0210 Now you are all set for Cadence and Hspice Every time you need to start working on Cadence do the following: source.cshrc.ic icfb& These are some useful Cadence and Hspice tutorials online: http://www.engr.sjsu.edu/~dparent/ee166/CDS_1.htm http://vlsi.wpi.edu/cds/ http://www.ee.washington.edu/class/cadta/hspice/ http://www.ece.orst.edu/~moon/ece323/hspice/

11. L 05 29Jan0211 Schematic Capture: Making the circuit Open the Library Manager (click tools on cadence window) Create a new library (say Trial) File > New >Library > Name >Attach existing file > Analog lib Create a cell view (say inverter) Click on library “Trial” > New >Cell view>Name> Tool: Schematic Composer A black window should be on your screen now. Familiarize yourself with the handy click buttons on the left. To add the parts of circuit Instance > Browse > Analog lib > Select component >select view as symbol.

12. L 05 29Jan0212 Add n-channel MOSFET (NMOS4) and a p-channel MOSFET (PMOS4). Set the properties, specifying width, length, and model. Add pins : IN OUT VDD GND Connect with wires Check and save

13. L 05 29Jan0213 Schematic Capture: Making the symbol Each circuit (schematic) created should have a symbol. The symbol is normally required when the same component is repeatedly used. This is most likely to happen when the bottom up design flow approach is used. To create a symbol: Click on library “Trial” > New >Cell view>Name (same as schematic)> Tool: Schematic Symbol Draw > Shape Add pins with same names as those in the schematic Check and Save

14. L 05 29Jan0214 Simulation To simulate the behavior of a component or a system a test bench is required. The best of going about that is creating a test library. Create another library (say Trial test) Create a new cell view (say Invtest) To add the parts of circuit Instance > Browse > Trial > Select Inverter >select view as symbol. Attach a voltage source (vdc) at the IN and at VDD Add a capacitor ( say cap = 0.01fF) Attach ground (gnd) to the pin GND Connect with wires Check and save

15. L 05 29Jan0215 There are various kinds of analyses possible, DC,AC,transient,etc. We will try DC analysis first. Click on Tools > Analog Environment (this opens another window) Analyses > DC > Specify the start and stop values and the component to be varied (In this case input voltage) Outputs > to be plotted > select on schematic > wire coming out of “OUT” pin and the one going into the “IN” pin. Setup > Simulator > HSPICE Setup > modelpath > type in /home/usrXXXX/cadence/IC/models > add above > select path > apply and run If everything is OK you should get an output in the form of the trasfer curve of Inverter.