2. TIMELINE FOR PRODUCTION 2  Need to be ready for production end next year  => submission of final mask set ~September 2015  Would like one more iteration with standard chips and some additional splits tests.  Need to submit this iteration in the spring to still have feedback before submission in September W. Snoeys 02/12/2014

3. ALPIDE chip Activity 2014201516 NovDecJanFebMarAprMa y JunJulAugSepOctNovDecJan Fabrication pALPIDE-2 Characterization pALPIDE-2 Design pALPIDE- 3 Fabrication pALPIDE3 Characterization pALPIDE-3 Design ALPIDE ALPIDE ER Validation ALPIDE Start production

4. REQUIREMENTS FOR ALPIDE3 4  Matrix  Resize to 3 cm  Front end (and sensor)  Multi Event Buffer  Priority encoder  Periphery  Biasing block (DACs)  Monitoring  High speed data transmission unit  Trigger and MEB control W. Snoeys 02/12/2014

5. MATRIX resize, pads and alignment marks 5  Need to adapt matrix to the full 3 cm (no more insensitive bands)  Finalize pads and alignment marks:  Final size and position  Modify pwell/sub pads over the matrix  Resize pads over the matrix  Horizontal routing on M5  Finalize alignment marks (now over pixel matrix at least for some) W. Snoeys 02/12/2014

6. FRONT END  Performance similar as before thinning and not affected by pads over the matrix  Band structure reflects different design options in the prototype chip  Noise << Threshold spread ~ 18 e 6

7. FRONT END & SENSOR 7  Sensor: maintain reverse biases, but some different geometries to be explored  Need to work on uniformity:  dimensioning of biasing transistors  simplify biasing  protection diodes (ideally 1 per front end bias to maximally protect the bias)  Electrical pulsing allows to establish functionality, but does not quite allow to really extract threshold and noise sufficiently accurately:  Injection capacitance small (~0.15fF) to minimize Cin  Uniformity  Other way to inject ?  Simplify biasing  Reduce filtering capacitance W. Snoeys 02/12/2014

8. FRONT END 8W. Snoeys 02/12/2014

9. FRONT END PULSING 9W. Snoeys 02/12/2014 Chip to chip comparison better just using the settings

10. MULTI EVENT BUFFER 10  From simulations (Adam) 3 memories inside the pixel would reduce dead time practically to zero.  Additional request: be able to allocate different memories to different types of trigger  Difficult to integrate with full-custom priority encoder (which would need optimization/correction anyway)  move to standard priority encoder with better form factor  implies difficulty to reach maximum footprint  Include routing for MEB control W. Snoeys 02/12/2014

11. BIASING BLOCK (DACs) 11  Need buffering capable to drive protection diodes (rail-to-rail opamp)  Add a few biases to support splits, also NMOS current (need same back bias as the matrix)  Would like to separate DACs for LVDS and include them with the LVDS block (these are not so critical)  Add on-chip monitoring for DACs (apart from DACMON-I and DACMON-V) pads to exterior (so link to ADC)  Yield control (disable switch per column ?)  Make control of this more compact  No easy translation to medium scale chip… W. Snoeys 02/12/2014

12. MONITORING 12  Strategy:  ADC referenced to bandgap  Maintain DACs referenced to VDDA  Monitor:  Power supplies  Biasing DAC outputs  Temperature  DAC: 8 b, ADC target 10 b W. Snoeys 02/12/2014

13. DATA TRANSMISSION 13  High Speed Data Transmission Unit/Output port Cfr Gianni & Alessandra et al Review: dec 15 or 16, proto tests when pALPIDEfs_V2 lot returns  PLL  Serializer  LVDS driver  Outer barrel parallel bus  Adapt M-LVDS with on-chip (programmable) termination to reduce clock skew and achieve double data rate at 40 MHz W. Snoeys 02/12/2014

14. pALPIDE3 Requirements for pALPIDE3 (ALPIDE fs prototype 3) Matrix implementation Final floorplan (30 mm × 15 mm) Final pads location Final pixel pitch and size In-pixel Multi Event hit storage (depth 3 MEB) Std cell based Priority Encoder Revised digital and analog routing Analog biasing and monitoring Digital periphery New module handling trigger management and MEB Revision of data path, re-factoring of Data Management Unit, optimization of data protocol Interfaces Data Transmission Unit (1.2 Gbps and 400 Mbps) Clocking distribution for OB module integration 02/12/14 gianluca.aglieri.rinella@cern.ch 14

15. RETICLE CONSTRAINTS 15 PALPIDE_fs pALPIDE_ms Final chip is 30x15 mm Dicing imposes dimensions for test structures. Small chips on the side, remaining width 1.760mm Could consider medium scale chip fitting in the floorplan as shown below, but… (see next page) W. Snoeys 02/12/2014

16. STRATEGY 16 Medium scale chip requires: total revision of analog bias block (different form factor) redefinition of interfaces pad ring, etc. -> significant overhead on aggressive planning -> also correspondence between full scale and small scale not clear, probably ok for medium scale, but not guaranteed Therefore tend to favor development of full scale standard chip (which has to be done anyway) in which we may include a small number of splits. If needed, a second engineering run will be submitted with a larger number of splits. This chip could be based on the ALPIDE_V2 to reduce the risk. W. Snoeys 02/12/2014

17. PLANNING 17W. Snoeys 02/12/2014