Presentation is loading. Please wait.

Presentation is loading. Please wait.

Thermodynamics in Chip Processing

Published byFrederica Richardson Modified over 9 years ago

Similar presentations

Presentation on theme: "Thermodynamics in Chip Processing"— Presentation transcript:

1 Thermodynamics in Chip Processing
Terry Ring

2

3 Silicon Wafers

4 Chip Feature Scaling

5 Moore’s Law please see

6 What is a semiconductor?
Metal Insulator Ceramic (oxides) Semiconductor Diamond Silicon Germanium Gallium Arsenide Host of others

7 Intrinsic Silicon Silicon has four valence electrons. When a group of Silicon atoms bond together to produce a pure lattice structure, the material is referred to as Intrinsic Silicon.

8 Silicon Doping This pure silicon configuration (intrinsic silicon) is a poor conductor because none of its electrons are available to serve as carriers of electric charge. The fabrication of integrated circuits requires that the substrate (the wafer surface) be somewhat conductive. This process is known as doping. Boron (B), Phosphorus (P), and Arsenic (As) are the most common dopant atoms used in the industry.

9

10 Dopant Chemistry By looking at the Periodic Table, we can determine the number of electrons that Boron and Phosphorus have in their outer orbit.

11 N-Type P Si Si Si Si Si P Si Si Si

12 P-Type Si Si Si B Si Si B Si Si Si

13 Anatomy of a Memory Chip
One Die or Chip

14 Building Blocks of the DRAM memory cell

15 READ +

16 WRITE -_

17 Basic DRAM memory cell - 1T
Transistor Capacitor

18 DRAM memory Array

19 MOSFET-Gate, Source, Drain Metal-Oxide-Semiconductor-Field-Effect-Transistors
A MOSFET is composed of three main components; a gate, a source, and a drain. The gate is a physical structure built on the wafer surface to control the opening and closing of a source-to-drain channel. To create this structure, a metal and oxide layer are formed on a semiconductor surface (MOS). The source and drain regions are just highly doped, shallow pockets in the wafer surface next to the gate.

20 The Transistor(continued)
Doing the dishes requires that we access a Source (or reservoir) of water. Channel (or pipe) connects the reservoir to the sink. Don’t want a continuous flow of water to our drain (or sink). . . Need a gate (or valve) to block the water flow.

21 Next Step Deposit Metal

22 Wafer with Photoresist
Lithography Light Source Light passes thru die mask Light imaged on wafer Stepper to new die location Re-image Mask Reduction Lens Wafer with Photoresist

23 MS&E vs ChE How is a Materials Science and Engineering Education Different from Chemical Engineering Education? Focus on Solids Processing What Crystal Structure Higher Purity Materials Impurities Control Properties Semiconductors Grain Boundaries Where atoms are in structure determines properties

24 Where Thermodynamics Comes into Chip Processing
Evaporation Rate during Spin Coating Evaporation Rate during Photoresist Drying Metal Physical Deposition Chemical Vapor Deposition Feed of TEOS Rxn of TEOS Etching - SiF4 vapor pressure CMP Solution Equilibria Dissolution/Precipitation

25 Wafer with Photoresist
Lithography Light Source Light passes thru die mask Light imaged on wafer Stepper to new die location Re-image Mask Reduction Lens Wafer with Photoresist

26 PhotoLythography PhotoResist UV light =193 nm 80 nm Line

27 Photoresist -Sales $1.2 billion/yr. in 2001
Resins phenol-formaldehyde, I-line Solvents Photosensitive compounds Polymethylmethacrylate or poly acrylic acid = 638 nm RED LIGHT diazonaphthoquinone Hg lamp, = 365 nm, I-line o-nitrobenzyl esters – acid generators Deep UV, = 248 nm, KrF laser Cycloolefin-maleic anhydride copolymer Poly hydroxystyrene =193 nm gives lines 100 nm = 157 nm F laser Additives

28 Photoresist Spin Coat wafer Dry solvent out of film Expose to Light
Develop Quench development Dissolve resist (+) or developed resist (-)

29 Spin Coating Cylindrical Coordinates Navier-Stokes Continuity

30 Newtonian Fluid- non-evaporating
If hois a constant film is uniform For thin films, h  -1 t-1/2

31 Evaporation Model - Heuristic Model
CN non-volatile, CV volatile e = evaporation rate of volatile component ei = kMA(Psolvent-I - 0) q = flow rate

32 Evaporation Rate What is Psolvent-i in a mixture?
Other solvents and non-volatile components fil = fiv equilibrium condition fiv =yiP fil = γ i xi Pisat ln γ i =GiE/(RT)

33 Vapor Pressure of 2 solvent mix
P =Σ γ i xi Pisat = γ 1 x1 P1sat + γ 2 x2 P2sat y1 =P1/P= γ 1 x1 P1sat /(γ 1 x1 P1sat + γ 2 x2 P2sat ) Pisat obtained from Normal Boiling Point & Heat of vaporization (Claperon Equation) Eqs a Margules equation, GE/(x1x2RT)=A21X1+A12X2

34 See MathCad Example Vapor Pressure of Solvent Mix.mcd
Binary Solvent Mixture Ternary mixture of Solvent plus Non-volatile Resin

35 Next Step Dissolve Edge of Photoresist
So that no sticking of wafer to surfaces takes place Wafers are stored in a rack on edge So that no dust or debris attaches to wafers Wafer with Photoresist

36 How would you set up this problem?
fil = fis equilibrium condition fis = γsi zi fsi fil = γli xi fli same a previous example of solvent mix ln γl i =GiE/(RT) same a previous example of solvent mix γli xi fli = zi γsi fsi γli xi = zi γsi Ψi Chapter 14 Ψi = exp{(ΔHisl/R)[(1/Tm) - (1/T)]} Chapter 14 ΔHisl =Heat of fusion, Tm melting temperature zi γsi=1 for ideal solid (misicible) zi= mole fraction of mix in solid

37 Break Second lecture is next What did we learn
Calculate the partial pressure Used to calculate the evaporation rate of a component of a solvent mixture Calculate the solubility of a solid in a solvent mixture

38 Lecture 2 Metal Deposition on the wafer
Wires to connect the transistors and capacitors To each other To outside world 2 Mb memory chip has > 1 km of wire 8 layers of wiring on top

39 Deposition Methods Growth of an oxidation layer Spin on Layer
Chemical Vapor Deposition (CVD) Heat = decomposition T of gasses Plasma enhanced CVD (lower T process) Physical Deposition Vapor Deposition Sputtering

40 Physical Vapor Deposition
Evaporation from Crystal (metal) Deposition on Wall

41 Physical Deposition Reactor
Wafers in Carriage (Quartz) Carrier Gasses enter Pumped out via vacuum system Furnace Metal evaporated Sublimation No liquid phase Furnace Vacuum Chamber at lower Temp s l v P V

42 Deposition Rate Ratei = Km A {Pi(TF) - Pi(TC)}
What is the sublimation partial pressure of metal as a function of temperature? fiv = fis equilibrium condition fis = γsi zi fsi= γsi zi Pisat exp[VMi(P - Pisat)/(RT)] Poynting Factor fiv =yiP

43

44 Metal Saturation Pressure
Sublimation Vapor Pressure Claperon Equation ΔHS is the heat of sublimation ΔHS = ΔHF + ΔHV solid to liquid then liquid to vapor

45 MathCad File Sublimation Vapor Pressure of Alloy.mcd

Download ppt "Thermodynamics in Chip Processing"

Similar presentations

FABRICATION PROCESSES

FABRICATION PROCESSES
Process Flow : Overhead and Cross Section Views ( Diagrams courtesy of Mr. Bryant Colwill ) Grey=Si, Blue=Silicon Dioxide, Red=Photoresist, Purple= Phosphorus.

Process Flow : Overhead and Cross Section Views ( Diagrams courtesy of Mr. Bryant Colwill ) Grey=Si, Blue=Silicon Dioxide, Red=Photoresist, Purple= Phosphorus.
CMOS Fabrication EMT 251.

CMOS Fabrication EMT 251.
Lecture 0: Introduction

Lecture 0: Introduction
Wally Dream Job.

Wally Dream Job.
VLSI Design Lecture 2: Basic Fabrication Steps and Layout

VLSI Design Lecture 2: Basic Fabrication Steps and Layout
Semiconductors What Is A Semiconductor? A semiconductor is a substance that has a lower conductivity than a metal and a higher conductivity than a non-metal.

Semiconductors What Is A Semiconductor? A semiconductor is a substance that has a lower conductivity than a metal and a higher conductivity than a non-metal.
Silicon Laser Shyam Sabanathan Chenjing Li Thannirmalai.

Silicon Laser Shyam Sabanathan Chenjing Li Thannirmalai.
Week 10a – Introduction to Semiconductors and Diodes

Week 10a – Introduction to Semiconductors and Diodes
Introduction to CMOS VLSI Design Lecture 0: Introduction

Introduction to CMOS VLSI Design Lecture 0: Introduction
MSE-630 Dopant Diffusion Topics: Doping methods Resistivity and Resistivity/square Dopant Diffusion Calculations -Gaussian solutions -Error function solutions.

MSE-630 Dopant Diffusion Topics: Doping methods Resistivity and Resistivity/square Dopant Diffusion Calculations -Gaussian solutions -Error function solutions.
P and n type semiconductors. Semiconductors Semiconductors are also referred to as metalloids. Metalloids occur at the division between metals and non-metals.

P and n type semiconductors. Semiconductors Semiconductors are also referred to as metalloids. Metalloids occur at the division between metals and non-metals.
Introduction to CMOS VLSI Design Lecture 0: Introduction

Introduction to CMOS VLSI Design Lecture 0: Introduction
Lecture 0: Introduction. CMOS VLSI Design 4th Ed. 0: Introduction2 Introduction  Integrated circuits: many transistors on one chip.  Very Large Scale.

Lecture 0: Introduction. CMOS VLSI Design 4th Ed. 0: Introduction2 Introduction  Integrated circuits: many transistors on one chip.  Very Large Scale.
The Deposition Process

The Deposition Process
Device Fabrication Example

Device Fabrication Example
Introduction Integrated circuits: many transistors on one chip.

Introduction Integrated circuits: many transistors on one chip.
Theory and Fabrication of Integrated Circuits Lecture. No. 04 Prof. Dr. Wajiha Shah.

Theory and Fabrication of Integrated Circuits Lecture. No. 04 Prof. Dr. Wajiha Shah.
Lecture 10.0 Photoresists/Coating/Lithography. Semiconductor Fab Land$0.05 Billion Building$0.15 Billion Tools & Equipment $1 Billion Air/Gas Handling.

Lecture 10.0 Photoresists/Coating/Lithography. Semiconductor Fab Land$0.05 Billion Building$0.15 Billion Tools & Equipment $1 Billion Air/Gas Handling.
ISAT 436 Micro-/Nanofabrication and Applications MOS Transistor Fabrication David J. Lawrence Spring 2001.

ISAT 436 Micro-/Nanofabrication and Applications MOS Transistor Fabrication David J. Lawrence Spring 2001.

Similar presentations

Ads by Google