1. Connector Differential Receiver 8 Channels 65 MHz 12 bits ADC FPGA Receive/buffer ADC data Format triggered Events Generate L1 Primitives Receive timing /clocks Data path interfaceFEM Optical GTM/Ethernet Detector signals DCM Trigger data FEM Block Diagram FEM Crate Diagram LL1 trigger

2. Signal cable input Trigger output HBD FEM Clock input

3. S-S+G S- Signal arrangement Use 2MM Hard Metric cable to move signals between preamp/FEM 2mm HM connector has 5 pins per row and 2mm spacing between pins and rows There are two types of cable configuration: *100 ohms parallel shielded cable 50 ohms coaxial cable Our choice is This gives us signal density 2mm x 10mm for every 2 signals. Same type of cables will be used for L1 trigger data.

4. HBD FEE 48 channels per FEM –3 signal cables to detector. –4 signal pairs to HBD LL1 crate – within the racks –Clock cable from interface to the FEM – within the crates (back) –6UX160mm card size Interface module –GTM (clock, L1 trigger etc.), Ethernet interface for slow download. –Control test pulse – don’t know the cable size yet. Data output module –1 optical module per card Crate has –16 FEMs –4 optical output modules –1 interface module HBD readout will fit into 3 6U crates HBD LL1 module potentially could fit into one 6U crate. Power – 5V digital, +4 analog, -3.3V analog – 1KW per crate (?) We will use a standard VME 6U crate mechanics with custom backplane. –We will bring the crates. Need space to route the signal cables to the FEM –Need to know how long is the cable routing path- Signal cables are custom made