1. 11 EENG 1920 Introduction to VHDL

2. 22 Hardware Description Language A computer language used to design circuits with text-based descriptions of the circuits. VHDL (VHSIC Very High Speed Integrated Circuit Hardware Description Language) is the industry-standard language used for programming PLDs.

3. 33 VHDL History Developed by defense contractors as a standard for programming circuits. Currently defined by IEEE Standard 1076- 1993. Related standard for certain data types is IEEE Standard 1164-1993.

4. 44 VHDL Used to describe the structure or behavior of hardware. Describes how the hardware should operate (modeling). Describes how how the hardware should be built (synthesis).

5. 55 VHDL In VHDL the designer enters text according to the syntax of the language. Syntax: The rules of construction, or “grammar”, of a programming language.

6. 66 Entity and Architecture Two basic constructs required for all VHDL code. The entity declaration describes the inputs and outputs. The architecture body defines the relationships between the inputs and outputs.

7. 77 VHDL Entity Defines the external aspects of the function. Each input or output is a port. –IN refers to a port used only for input. –OUT refers to a port used only for output

8. 8 VHDL Entity Declaration 8 ENTITY majority_vote IS PORT( a, b, c: IN BIT; y : OUT BIT); END majority_vote;

9. 99 VHDL Architecture Body ARCHITECTURE maj_vote OF majority vote IS BEGIN y <= (a and b) or (b and c) or (a and c); END maj_vote;

10. 10 Boolean Operators in VHDL AND, OR, NOT, NAND, NOR, XOR, and XNOR are represented as written. VHDL has no order of precedence for Boolean operators. Expressions must be written explicitly with parentheses.

11. 11 Boolean Operators Example Y <= (a and(not b)) or ((not a) and b and (not c)); Y <= not((a and b) or ((not a) and (not c)) or d);

12. Using Xilinx ISE 8.1i 12

13. Using Xilinx ISE 8.1i 1.Start/All Programs 2.Locate Modelsim / license Wizard(Click) 13

14. Using Xilinx ISE 8.1i 3.Click Continue 14

15. Using Xilinx ISE 8.1i 4. Click OK (Window should be as shown) 15

16. Using Xilinx ISE 8.1i 5. Click Yes 16

17. Using Xilinx ISE 8.1i 6. Click OK 17

18. Using Xilinx ISE 8.1i 7.Click OK 8.Repeat steps 1-7 one more time. 18

19. Using Xilinx ISE 11.1 19

20. Using Xilinx ISE 11.1 1.Before beginning, license your Xilinx ISE. 2.Double click on Xilinx ISE 11.1. 3.Click oK on “NO license” window. 4.Click on Help. 5.Click on Manage license. 6.In the XILINX_LICENSE_FILE type: 27001@ceng-licmgr.eng.unt.edu27001@ceng-licmgr.eng.unt.edu 7.Click Set 8.In the LM_ LICENSE_FILE type: 27000@ceng-licmgr.eng.unt.edu27000@ceng-licmgr.eng.unt.edu 9.Click Set 10.Click Close 20

21. 21 VHDL Entry If we choose VHDL as the design entry, we can use any text editor tool to create and edit the VHDL code and then add the VHDL file into an ISE project. For example, you can open Notepad, type (or cut and paste) in the following VHDL code, and save the model as a file such as ccb2.vhd (be sure to remove any.txt extension that Notepad adds at the end of the file name). library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_ARITH.all; use IEEE.std_logic_UNSIGNED.all; entity CCB2 is Port ( Din0 : in STD_LOGIC; Din1 : in STD_LOGIC; Sel : in STD_LOGIC; Dout : out STD_LOGIC); end CCB2; architecture Behavioral of CCB2 is begin Dout <= (Din0 and not Sel) or (Din1 and Sel); end Behavioral;

22. 22 New Project 1.Start Xilinx ISE 8.1i project navigator by double clicking the ISE icon on your desktop. 2.Click on File and select New project

23. 23 Project window 3. Name your project and project location, then click next

24. 24 New Project Wizard 4. The Spartan Starter Kit PCB board uses a Xilinx Spartan3 XCS200 FPGA chip which is packaged in a flat thin 256-pin (FT256) ball Grid Array. Set these values the new project Wizard window,

25. 25 Create New Sou rce 5. We will add our sources to this project later, so here we skip the following two steps (create source and add source). Click on Next.

26. 26 Project Summary 6. Check the project summary and click Finish

27. 27 VHDL 7. Now we will create a blank sheet for schematic capture. First, click the project and new Source menu.

28. 28 VHDL 2. Click VHDL Module and type in the name for your schematic. Select add to project before clicking Next.

29. VHDL 29 We will program this circuit in VHDL

30. 30 VHDL 3. Define the Module

31. 31 VHDL 4. Check over the summary and click on Finish

32. 32 VHDL 5. Now an empty VHDL file has been created which already has the entity and skeleton of the architecture. Type in your VHDL codes in architecture and complete your design. After you finish the design, save the file.

33. 33 Design Verification

34. 34 Design Verification 1. Select Behavioral Simulation and double click on CCB2.sch

35. 35 Design Verification 2. Expand ModelSim Simulator and double click on Double click on Simulate Behavioral Model

36. 36 Design Verification 3. This is the window that appears

37. 37 Design Verification 4. At VSIM2> type in force signal-name state-value time as shown. Enter after run will run the simulation.

38. 38 Synthesize the Design

39. 39 Synthesize the Design 1. Click on Xilinx-ISE to get Design Summary and select as shown by the arrows

40. 40 Synthesize the Design 2. Right click as shown by the arrow and click on run. A design is produced.

41. 41 Synthesize the Design 3. Select Project/New Source

42. 42 Synthesize the Design 4. Click as shown, type in the File name and click on Next.

43. 43 Synthesize the Design 5. This window appears, click on Next.

44. 44 Synthesize the Design 6. This window appears, click on Finish

45. 45 Synthesize the Design 7. The design summary appears, click as shown by the arrow. We will assign pin numbers

46. 46 Synthesize the Design 8.

47. 47 Synthesize the Design 9.After saving the pin arrangement, click on OK

48. 48 Synthesize the Design 10. After the constraints file has been completed, right click on Implement Design and select Run.

49. 49 Synthesize the Design 11. Right click on Generate Programming file and select Run

50. 50 Synthesize the Design 12. Finally, an FPGA configuration data (*.bit) file is generated.

51. 51 Download and Verify The Design

52. 52 Download and Verify The Design This is the last step in the design verification process. This section provides instructions for downloading the MUX design onto the Spartan 3 PCB. 1) Connect the 5V DC power cable to the power input on the demo board (J4). (note: you may see a sequence of numbers begin to flash on the 7- segment LEDs, this is just a test configuration stored in the flash memory on the PCB and you can manipulate the various switches and button, except for the PROG button, on the PCB to see the operation of the LEDs and 7-segment displays). 2) Connect the download cable between the PC parallel port and the demo board (J7). 3) Select Synthesis/Implementation from the drop-down list in the Sources window and select Mux_Schematic or Mux_vhdl (or whatever you named you design) in the Sources Window. In the Processes window, expand the Generate Programming File process and double-click the Configure Device (iMPACT) process.

53. 53 Download and Verify The Design 1. Processes window, expand the Generate Programming File process and double-click the Configure Device (iMPACT) process.

54. 54 Download and Verify The Design 2. iMPACT opens and the Configure Devices dialog box is displayed. In the Welcome dialog box, select Configure devices using Boundary-Scan (JTAG). Verify that Automatically connect to a cable and identify Boundary-Scan chain is selected. Click Finish.

55. 55 Download and Verify The Design 3. When programming is complete, the Program Succeeded message is displayed.

56. 56 Download and Verify The Design 4. Close iMPACT without saving. Your design is downloaded into the FPGA and you can begin to verify the design by manipulating swithes/buttons and observing LEDs as specified in your design.