1. Learning to Design Counters
Today:
First Hour: Designing a Counter
Section 7.2 of Katz’s Textbook
In-class Activity #1
Second Hour: More on Counters
Section 7.3 of Katz’s Textbook
In-class Activity #2

2. Recap: Flip Flops
Given the current state, and its inputs. What is its next state?
S R Q Q+ J K Q Q+ D Q Q+ T Q Q+ 1 X 1 1 1
X = that input is illegal

3. Excitation Tables
Suppose we want to change from state Q = 1 to state Q+ = 0
Q Q+ R S J K T D
0 0
0 1
1 0
1 1
X 1
1 0
RESET or TOGGLE
TOGGLE
RESET
What should be the input (excitation) for a
T flip-flop or a D flip-flop
to make this change?
J-K flip-flop
Why is JK = X1? Because either JK = 01 or JK = 11 will change state 1 to state 0. Similar reasoning yields the other entries.

4. Synchronous Finite-State Machines
Described by State Diagrams, much the same way that combinational logic circuits are described by Boolean Algebra.
Current
State
New
State
Current Input(s)
Change of state happens only on the clocking event

5. Example: 3-bit Binary Up-Counter
000
000
001
001
010
010
Each circle corresponds to a state
The label inside each circle describes the state
111
111
011
011
Arrows represent state transitions
110
110
101
101
100
100
No labels on arrows, since the counter has no inputs

6. State Transition Table
The Table is equivalent to the Diagram
Current Next
State State
C B A C+ B+ A+
The “+” superscripts indicate new values.
000
001
010
110
101
100
111
011
State Diagram
State Transition Table

7. Picking a Flip-Flop Let's use T F/Fs How many do we need? 3
Current Next
State State
C B A C+ B+ A+
Let's use T F/Fs
How many do we need? 3
State Transition Table
Neat Fact: we could have picked any other type or more than one type

8. Flip-Flop Input Table
What T F/F inputs are needed to make them change to the next state?
Current Next Flip-Flop
State State Inputs
C B A C+ B+ A+ TC TB TA
Q Q+ T
0 0 0
0 1 1
1 0 1
1 1 0
Excitation Table
State Transition Table
F/F Input Table

9. From Table to K-maps Current Flip-Flop State Inputs C B A TC TB TA C B A 1 TA
TA = 1 C B A 1 TB
TB = A C B A 1 TC
TC = A•B
Re-drawn Table

10. Build the Circuit! TB = A TA = 1 TC = A B Timing Diagram +5V 100
CLK
\Reset Q S R QA QB QC
Count
+5V
TC = A B
Timing Diagram
Count
\Reset Q C B A
100

11. Complex Counters The generalized design process has four steps
1. Draw a State Transition Diagram
2. Derive the State Transition Table
3. Choose a Flip-Flop to Implement the Design
4. Derive the Flip-Flop Input Functions
Note: this list skips step 3 on page 341 of the Katz.

12. Design a counter with the sequence 000, 010, 011, 101, 110, and wrap
Complex Counters
Design a counter with the sequence 000, 010, 011, 101, 110, and wrap
000
010
101
110
011
1. Derive the State Transition Diagram
State Diagram

13. 2. State Transition Table
Tabulate the Next State for each State in the Diagram
Current Next
State State
C B A C+ B+ A+
000
010
101
110
011
X X X
Note the use of Don't Care conditions
State Diagram
State Transition Table

14. Suppose we choose T Flip-Flops to implement the design
3. Choose F/Fs
Suppose we choose T Flip-Flops to implement the design
Q Q+ T
0 0 0
0 1 1
1 0 1
1 1 0
Excitation Table

15. State Transition Table
4. Derive the F/F Inputs
Current Next Flip-Flop
State State Inputs
C B A C+ B+ A+ TC TB TA
X X X
X X X
X X X
State Transition Table
F/F Input Table
Q Q+ T
0 0 0
0 1 1
1 0 1
1 1 0
Excitation Table
X X X

16. Simplify Current Flip-Flop State Inputs C B A TC TB TA 0 0 0 0 1 0
X X X
X X X
X X X
Re-drawn Table X
X X 1 C B A 1 TA
TA = A·B·C + B·C X
X X 1 C B A 1 TB
TB = A + B + C X
X X 0 TC C B A 1
TC = A·C + A·C
= A  C

17. Build The Circuit! TB = A + B + C TC = A  C TA = A·B·C + B·C TC T CLKQ S R
Count TB C \C B A \B \A TA
\Reset

18. Do Activity #1 Now
Q Q+ T
0 0 0
0 1 1
1 0 1
1 1 0
Excitation Table
For T F/F TC T
CLK Q S R
Count TB C \C B A \B \A TA
\Reset
Note: This is a just a cleaner way to sketch the circuit
Works properly in LogicWorks
When we work with hardware,
we have to explicitly wire these connections

19. When a counter “wakes up”…
Random power-up states
The counter may be in any possible state
This may include skipped states
In the counter example from the previous lecture, states 001, 100, & 111 were skipped
It is possible that the random power-up state may be one of these
Can we be sure the counter will sequence properly?
State Diagram
001
100
000
010
011
101
110
111

20. Don't-Care Assignments
K-map minimization
Flip-Flop Input Functions
Present
State
Toggle
Inputs
C B A TC TB TA
The Xs for the Toggle Inputs were set by the K-maps to minimize the T Flip-Flop Input Functions

21. Skipped State Behavior
Sequences from K-map minimization
State Diagram
001
100
000
010
011
101
110
111
When these K-map assignments are made for the Xs, it results in
001  100, 100  111, and 111  001
Therefore, the counter might not sequence properly

22. Self-Starting Counter
111
000
010
011
101
110
001
100
A self-starting counter is one that transitions to a valid state even if it started off in any other state.
Many possible choices & tradeoffs

23. Counter Reset Solution
Use a separate Reset switch
Power-ON Reset Circuit: Reset signal is 1 briefly while circuit is powered up. This signal is used to reset all flip-flops.
+5V +5
High threshold
Reset
Time t 5e
-t/RC P W R C
To FF
Resets R

24. Using other Flip-Flops
Just use the correct Excitation Table in setting up the flip-flop input function table.
The input functions must be appropriate for the flip-flop type (no bad input patterns).

25. Fill in flip-flop input functions based on J-K excitation table
Example #1:J-K F/F
3-bit Counter: 0  2  3  5  6  0 …
Present
State
Next
State
Flip-Flop
Inputs
Q Q+ J K X X
1 0 X 1
1 1 X 0
Q+ = J Q' + K' Q
J-K Excitation Table
C B A C+ B+ A+ JC KC JB KB JA KA
X X X
X X X
X X X
0 X 1 X 0 X
X X X X X X
0 X X X
1 X X 1 X 0
X X X 1
X 1 X X
Flip-Flop Input Functions
Fill in flip-flop input functions based on J-K excitation table

26. Input Function K-Maps JC 0 0 X X X 1 X X KC X X 1 X X X X 0 JB 1 X X XCB 00 01 11 10 A 1 JC
X X
X X X KC
X X X
X X X 0 JB
1 X X X
X X X 1 JA X
X X X X KB
X X KA
X X 1
C B A C+ B+ A+ JC KC JB KB JA KA
X 1 X 0 X
X X X X X X X X X
X X X
X X 1 X 0
X X X X X X X X X
X X X 1
X 1 X X
X X X X X X X X X
Flip-Flop Input Functions
Present
State
Next
Flip-Flop Input
Inputs
= A
= A’
= 1
= A + C
= B C'
= C

27. J-K Flip-Flop Counter Resulting Logic Level Implementation:
CLK J K Q A \ C KB B
+5V JA
Count
Resulting Logic Level Implementation:
2 Gates, 10 Input Literals + Flip-Flop Connections

28. Example #2: D F/F Simplest Design Procedure
D F/F inputs are identical to the next
state outputs in the state transition table
C+ B+ A+ columns are identical to DC DB DA columns
C B A C+ B+ A+ DC DB DA
X X X X X X
X X X X X X
X X X X X X

29. D Flip-Flop Counter Resulting Logic Level Implementation:
CLK D Q A \ DA DB B C
Count
Resulting Logic Level Implementation:
3 Gates, 8 Input Literals + Flip-Flop connections

30. Comparison T F/Fs well suited for straightforward binary counters
But yielded worst gate and literal count for this example!
J-K F/Fs yielded lowest gate count
Tend to yield best choice for packaged logic where gate count is key
D F/Fs yield simplest design procedure
Best literal count
D storage devices very transistor efficient in VLSI
Best choice where area/literal count is the key

31. Do Activity #2 Now For Next Class:
Due: End of Class Today. NO EXTENSION TODAY
RETAIN THE LAST PAGE(S) (#3 onwards)!!
For Next Class:
Bring Randy Katz Textbook, & TTL Data Book
Required Reading:
Sec 7.4, 7.6 of Katz
This reading is necessary for getting points in the Studio Activity!