1. CEC 220 Digital Circuit Design Counters Using S-R and J-K Flip-Flops Monday, November 2 CEC 220 Digital Circuit Design Slide 1 of 19

2. Lecture Outline Monday, November 2 CEC 220 Digital Circuit Design A multi-Function Shift-Register Counter Design Using S-R & J-K FFs Slide 2 of 19

3. 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 SI Sh L Clk A Multi-Function Shift Register InputsNext StateAction Sh (Shift)L (Load) 00Hold 01Parallel Load 1XSIShift Right A multi-Function Shift-Register SO Monday, November 2 CEC 220 Digital Circuit Design Slide 3 of 19

4. SI Sh L Clk Sh = 0 and L = 0 Hold 0 A multi-Function Shift-Register Monday, November 2 CEC 220 Digital Circuit Design Slide 4 of 19 Sh  LL

5. SI Sh L Clk Sh = 0 and L = 1 Parallel Load 0 1 A multi-Function Shift-Register Monday, November 2 CEC 220 Digital Circuit Design Slide 5 of 19 Sh  LL

6. SI Sh L Clk 1 0 1 Sh = 1 and L = 0 or 1 Right Shift or A multi-Function Shift-Register Monday, November 2 CEC 220 Digital Circuit Design Slide 6 of 19 Sh  LL LL

7. Counters Using S-R and J-K Flip-Flops Design with S-R Flip-Flops Monday, November 2 CEC 220 Digital Circuit Design Recall the previous six state counter  Repeat the design using S-R flip-flops 010 000 100 111 011 QQ+Q+ S RJ KTD 000 X 00 011 01 X11 100 1X 110 11X 0 01 Excitation Table We will need 3 FFs Slide 7 of 19

8. Counters Using S-R and J-K Flip-Flops Design with S-R Flip-Flops Monday, November 2 CEC 220 Digital Circuit Design State Transition Table Present State Next State 000100 001XXX 010011 011000 100111 101XXX 110XXX 111010 Present State Next State Flip-Flop Inputs 000100 001XXX 010011 011000 100111 101XXX 110XXX 111010 10 0X XX 0X X0 XX XX 01 Present State Next State 000100 001XXX 010011 011000 100111 101XXX 110XXX 111010 0X XX X0 01 10 XX XX X0 Present State Next State 000100 001XXX 010011 011000 100111 101XXX 110XXX 111010 0X XX 10 01 10 XX XX 01 QQ+Q+ S R 000 X 011 0 100 1 11X 0 Slide 8 of 19

9. Counters Using S-R and J-K Flip-Flops Design with S-R Flip-Flops Monday, November 2 CEC 220 Digital Circuit Design 01 001X 01XX 1100 100X 01 0000 01XX 11X1 10XX 01 0001 01XX 110X 10XX 01 00X0 01XX 1110 100X 01 0001 01XX 1100 101X 01 00X0 01XX 1111 100X Slide 9 of 19

10. Counters Using S-R and J-K Flip-Flops Design with S-R Flip-Flops Monday, November 2 CEC 220 Digital Circuit Design Circuit Design Clk Slide 10 of 19

11. Counters Using S-R and J-K Flip-Flops Design with J-K Flip-Flops Monday, November 2 CEC 220 Digital Circuit Design Recall the previous six state counter  Repeat the design using J-K flip-flops 010 000 100 111 011 QQ+Q+ S RJ KTD 000 X 00 011 01 X11 100 1X 110 11X 0 01 Excitation Table We will need 3 FFs Slide 11 of 19

12. Counters Using S-R and J-K Flip-Flops Design with J-K Flip-Flops Monday, November 2 CEC 220 Digital Circuit Design State Transition Table Present State Next State 000100 001XXX 010011 011000 100111 101XXX 110XXX 111010 Present State Next State Flip-Flop Inputs 000100 001XXX 010011 011000 100111 101XXX 110XXX 111010 1X 0X XX 0X X0 XX XX X1 Present State Next State 000100 001XXX 010011 011000 100111 101XXX 110XXX 111010 0X XX X0 X1 1X XX XX X0 Present State Next State 000100 001XXX 010011 011000 100111 101XXX 110XXX 111010 0X XX 1X X1 1X XX XX X1 QQ+Q+ J K 000 X 011 X 10X 1 11X 0 Slide 12 of 19

13. Counters Using S-R and J-K Flip-Flops Design with J-K Flip-Flops Monday, November 2 CEC 220 Digital Circuit Design 01 001X 01XX 110X 100X 01 00X0 01XX 11X1 10XX 01 0001 01XX 11XX 10XX 01 00X0 01XX 1110 100X 01 0001 01XX 11XX 101X 01 00XX 01XX 1111 10XX Slide 13 of 19

14. Counters Using S-R and J-K Flip-Flops Design with J-K Flip-Flops Monday, November 2 CEC 220 Digital Circuit Design Circuit Design Clk Slide 14 of 19

15. Counters Using S-R and J-K Flip-Flops Design with J-K Flip-Flops Monday, November 2 CEC 220 Digital Circuit Design Where so states 1, 5, and 6 go? State Transition Table Present State Next State Flip-Flop Inputs 0001001X0X0X 001XXXXXXXXX 0100110XX01X 0110000XX1X1 100111X01X1X 101XXXXXXXXX 110XXXXXXXXX 111010X1X0X1 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 0 0 0 1 1 1 1 0 1 0 1 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Slide 15 of 19

16. Now determine how these FF input choices effects the “don’t care” state transitions Counters Using S-R and J-K Flip-Flops Design with J-K Flip-Flops Monday, November 2 CEC 220 Digital Circuit Design Where so states 1, 5, and 6 go? State Transition Table Present State Next State Flip-Flop Inputs 000100100001 001XXX110101 010011000011 011000010111 100111101011 101XXX111011 110XXX001011 111010011011 100 JKQ+Q+ 00Hold 01Reset 10Set 11Toggle 010 111 Slide 16 of 19

17. Counters Using S-R and J-K Flip-Flops Design with J-K Flip-Flops Monday, November 2 CEC 220 Digital Circuit Design Where so states 1, 5, and 6 go? 010 000 100 111 011 001 101 110 Slide 17 of 19

18. Counters Using S-R and J-K Flip-Flops Monday, November 2 CEC 220 Digital Circuit Design Comparing the two Designs Clk Using J-K Flip-Flops Using S-R Flip-Flops Slide 18 of 19

19. Next Lecture Monday, November 2 CEC 220 Digital Circuit Design VHDL in sequential logic Slide 19 of 19