1. Chapter 6 Copyright © 2004 The McGraw-Hill Companies, Inc. All rights reserved. High-Speed CMOS Logic Design

2. 6.1 INTRODUCTION

3. 6.1 Introduction

4. 5.6.1 Basic Bistable Circuit

5. 6.1 Introduction

6. 6.2 SWITCHING TIME ANALYSIS

7. 6.2 Switching Time Analysis

8. Propagation delay time for Low-to-High case : for High-to-Low case : average propagation delay time : (6.1) (6.2) (6.3) 6.2 Switching Time Analysis

9. NMOS device (pull-down) (n-channel device saturation current : ) propagation delay time : & (Chapter 5) therefore (6.4a) (6.4b) 6.2 Switching Time Analysis

10. Linear region operation 2.5.2 Current Equations for Velocity-Saturated Devices (2.25)

11. Saturation region operation Limiting cases : ( ) (2.26) (2.27) (2.28) (2.29) 2.5.2 Current Equations for Velocity-Saturated Devices

12. PMOS device (pull-down) (p-channel device saturation current : ) propagation delay time : therefore (6.5a) (6.5b) 6.2 Switching Time Analysis

13. refer to the example 6.1 (p.254) equvalent resistance for SPICE simulation sheet resistance : total resistance (6.6) 6.2 Switching Time Analysis

14. 6.2.1 Gate Sizing Revisited-Velocity Saturation Effects

15. 5.2.3 Voltage Transfer Characteristics (VTC) of CMOS Gates

16. 6.2.1 Gate Sizing Revisited-Velocity Saturation Effects

18. 6.3 DETAILED LOAD CAPACITANCE CALCULATION

19. 6.3 Detailed Load Capacitance Calculation (6.7)

20. 6.3.1 Fanout Gate Capacitance

21. 2.8 Capacitances of the MOS Transistor

22. 2.8.1 Thin-Oxide Capacitance Total capacitance of the thin-oxide : Examples : i) technology, oxide thickness ii) process, with (2.34)

23. 2.8.1 Thin-Oxide Capacitance

24. Total fanout capacitance : Total input capacitance for 0.13 technology therefore, redefine (6.8) (6.9) 6.3.1 Fanout Gate Capacitance

25. For an inverter total fanout capacitance : For NANDs, NORs, or other complex gates 6.3.1 Fanout Gate Capacitance

26. 6.3.2 Self-Capacitance Calculation

28. Copyright © 2004 The McGraw-Hill Companies, Inc. All rights reserved. Miller theorem (for voltages)

29. Total self-capacitance of the inverter Effective capacitance per width (6.10) 6.3.2 Self-Capacitance Calculation

31. Self-capacitance at the ouput node (6.11) 6.3.2 Self-Capacitance Calculation

33. Wire capacitance (6.12) 6.3.3 Wire Capacitance

34. 6.7 Summary Propagation delay : Driving resistance : Load capacitance : Input capacitance : Self-capacitance : Wire capacitance : Total delay :

35. 6.4 IMPROVING DELAY CALCULATION WITH INPUT SLOPE

36. 6.4 Improving Delay Calculation with Input Slope (6.13)

37. 6.4 Improving Delay Calculation with Input Slope

45. Total delay for ramp input (according to the example above) therefore (6.14) 6.4 Improving Delay Calculation with Input Slope

46. (6.15)

47. 6.5 GATE SIZING FOR OPTIMAL PATH DELAY

48. 6.5.1 Optimal Delay Problem

51. Input capacitance of gate effective output resistance therefore, time constant (6.16) (6.17) (6.18) 6.5.2 Inverter Chain Delay Optimization – FO4 Delay

53. Delay time ratio of self-capacitance to input capacitance (6.19) (6.20) 6.5.2 Inverter Chain Delay Optimization – FO4 Delay

55. Total delay time delay term depend upon the size of inverter j 6.5.2 Inverter Chain Delay Optimization – FO4 Delay

57. Using Figure 6.22 Delay time (using ) gate : total :, (6.21) (6.22) (6.23) 6.5.2 Inverter Chain Delay Optimization – FO4 Delay

60. 6.5.3 Optimizing Paths with NANDs and NORs

61. Total delay for NAND chain for NOR chain Intrinsic time constants for NAND for NOR (6.24) 6.5.3 Optimizing Paths with NANDs and NORs

63. Total delay Delay through stages j and j+1 (6.25) 6.5.3 Optimizing Paths with NANDs and NORs

64. Delay through stages j+1 and j+2 (6.25) 6.5.3 Optimizing Paths with NANDs and NORs

65. 6.6 OPTIMIZING PATHS WITH LOGICAL EFFORT

66. Total delay Delay equation ; logical effort ; fanout ; parastic term (6.25) 6.6.1 Derivation of Logical Effort

69. Parameters - LE values 6.6.1 Derivation of Logical Effort

70. Parameters - LE values (using capacitance ratios) (using equvalent resistances) (using capacitance ratios) (using equvalent resistances) 6.6.1 Derivation of Logical Effort

72. Paramters - P values for NAND for NOR 6.6.1 Derivation of Logical Effort

74. 6.6.2 Understanding Logical Effort

75. 6.6.3 Branching Effort and Sideloads

76. 6.7 SUMMARY

77. 6.7 Summary Propagation delay : Driving resistance : Load capacitance : Input capacitance : Self-capacitance : Wire capacitance : Total delay :

78. 6.7 Summary Inverter delay equation : where, Intrinsic time constants

79. 6.7 Summary Normalized delay equation : where LE(Logical Effort) for inverter, NAND2, and NOR2 Path effort

80. 6.7 Summary Optimal stage effort : Gate sizing based on optimal stage effort Normalized delay :