1. EECS 270: Inside Logic Gates (CMOS)
Prof. Igor Markov EECS

3. Logic Circuits Below Gates
Gates are convenient logic abstractions
Shield you from manufacturing technology
Are made of smaller components that perform independent electrical tasks
Smaller components: transistors
Types of transistors: MOS,bipolar,Shottky,…
Logic families (CMOS, TTL, ECL, CML)
Ways of making gates out of transistors
TTL was popular until the early 1990s
Now CMOS is by far the most popular

4. Transistors: Basic Ideas
A transistor is a 3-terminal switch
MOS
Gate, source, and drain
Gate voltage controls resistance between source and drain
Bipolar
Base, emitter and collector
Base current controls current from emitter to collector

5. MOS (Metal-Oxide Semiconductor)
For 5V power supply
Logic 0 (low): 0-1.5V; Logic 1(high): 3.5-5V
Smaller power-supply voltage used today to reduce power consumption
Uses SiO2 (oxide) as insulator
Metal contacts for terminals
Tungsten (W) for vertical plugs (vias)
Horizontal wires
Cu (now), Al (2+ years ago)
gate
source
drain

6. Field Effect Gate is insulated from source & drain
Gate voltage creates an electric field
increases or decreases resistance between source and drain
MOSFET (MOS Field-Effect Transistor)
gate
source
drain

7. CMOS (Complementary MOS)
Two types of MOS xtors
n-channel MOS (nMOS)
p-channel MOS (pMOS)
pMOS transistors
High V on source
Low V on gate  high V on drain
nMOS transistors
Low V on source
High V on gate  low V on drain
CMOS inverter (2 xtors)

8. CMOS Inverter
Match pMOS & nMOS xtors
VDD
VOUT
VIN
VGND

9. More CMOS Gates NAND (4 xtors) NOR (4xtors)
When A or B are low, OUT is high
Else OUT is low
NOR (4xtors)
When A and B are low, OUT is high
Else, OUT is low
Pull-up & pull-down networks

10. NOR Gate in CMOS

12. Solving Basic CMOS Problems
Recognizing incorrect CMOS gates
Recognizing the function of a correct CMOS gate
Key to solving these problems
Simulation for all input values
Gates are small, simulation is easy
Do not worry about gate layout

13. Simulation Simulate for each input combination
A single conflict between pull-up and pull-down networks  the gate is broken
Build the truth table of the gate 1 1 1

14. Characteristics of CMOS Gates
Area, #transistors
NAND is 2x more expensive than NOT
Sometimes larger circuits have compact implementations: AOI gate (see textbook)
Drive strength
Larger transistors can drive longer wires
Delay
Power consumption