1. Encrypted Transaction with Triple DES
Team W2
Yervant Dermenjian (W21) Taewan Kim (W22)
Evan Mengstab (W23)
Xiaochun Zhu (W24)
Objective: To implement a secure credit card transaction using 3DES encryption using Kerberos-style authentication.
Design Manager: Rebecca Miller
Final Presentation April 28, 2004

2. Project Description
Implement Triple DES Encryption/Decryption for both host and client ends using 0.18μ CMOS technology
Use Kerberos-style authentication
Encrypt User Information as data using CC# and Pin as Keys
Transaction Authorizer decrypts using CC# and Pin (which they know)
Credit Card Number and PIN are never transmitted, but are essential to authenticate
Attain speeds appropriate for application in
Automated Teller Machines (200MHz)
Integrate Encryption/Decryption into
ATM transaction
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3. Security In Making Purchases
Point-of-sale terminals transmit your name,
credit card number, and expiration dates
‘in the clear’
Identity theft is a growing problem
Credit and charge card fraud costs cardholders and issuers hundreds of millions of dollars each year
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4. Triple Data Encryption Standard
Difficult to decipher for large encryption keys
Symmetric Key Cipher – encryption & decryption use same key
Based on DES – a very trusted cipher
MasterCard requires all ATMs be 3DES compliant by April 1, 2005
Accepted as the new
standard for federal
agencies in 1999
Finalist for the 2001
Advanced Encryption
Standard
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5. Kerberos-style Authentication
Provides authentication without transmitting sensitive information.
Encrypt card expiration date using credit card number and secret PIN as encryption key.
The data payload is arbitrary. Only the cardholder and card acquirer have the key.
Using Kerberos-style authentication, we transmit encrypted information that can be verified by the card authorizer without actually containing sensitive information
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6. Unencrypted Card# + PIN
System Integration
Triple DES Compliant
Unencrypted Card# + PIN
Verified
Verified
OK!
Encrypted Card# + PIN
Encrypted Card# + PIN
Sensitive information never transmitted
Uses existing cards and phone network
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7. How It Works
Transmit: name, merchant, price, encrypted expiration date
Card company has CC# and PIN to decrypt packet
If expiration date matches, purchase is approved
CC# and PIN are never transmitted, but essential to authenticate
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8. The 3DES Algorithm Overview DES vs. 3DES Stages
Block Cipher - acts on a 64-bit block of plaintext
Converts it into a 64-bit block of cipher text using a 56-bit key
Specified in FIPS Pub 46-3
Symmetric Key Cipher – encryption & decryption use same key
DES vs. 3DES
3DES applies 3 stages of DES with a separate key for each stage
Total key length in 3DES is 56 bits x 3 keys = 168 bits
Stages
Stage 1: Encrypt plaintext with Key 1
Stage 2: Decrypt cipher text from Stage 1 with Key 2 (produces new cipher text)
Stage 2: Encrypt cipher text from Stage 2 with Key 3
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9. 3DES Algorithm Flowchart (I)
Encryption
DES
DES-1
Plain Text K3
Cipher Text K1 K2
DES-1
DES
DES-1
Decryption
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10. 3DES Algorithm Flowchart (II)
64 bit plain Text
Extension
32 bit bit
Left Half
Initial Permutation
Sub
key
48 Bit XOR
16 Rounds
Encryption
S Box
32 Bit XOR
Final Permutation
Right Half
Single
Round
cipher Text
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11. 3DES Algorithm Flowchart (III)
Key Schedule
56bit Key
Initial Permutation
I=1
I=I+1
Left/Right Half 28 bits
Left Barrel Shift N
I=16?
Final Permutation Y
Ready
48 bit Sub-key [ I ]
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12. Design Process Verification of 3DES in C Verilog Verification
Behavioral
Verification
Verilog
Initial Architecture
Key2 56 ’ b
SRAM
Barrel
Shifter I:
0,0,1,1,1,1,1,1,0,1,1,1,1,1,1,0 PC - 2
(wiring)
Key set
Current
and next
keys
2 x 48
Register 48 32 1
XOR
Expansion
b 48
Plaintext 64
R[I]
L[I] S
box
8x4x16x4
ROM
L[I 1]
R[I
b Register P
Key1,3
b output
b input
demux 16
b ROM IP
mux
Verilog Verification
Structural
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13. Architecture Development1 st
Architecture Revision
KeySub 56 ’ b
Register 32
b input
demux
Enc_ShiftL
Dec_ShiftR IP -
wiring PC 2
Wiring
>48
Text 64
Expand S
Box
512 x 4 P 48
>32
PC (wiring)
Key Latch
2:1
mux
R_L
Sub_rnd
e/d
D1/D1
txt_in
ready
key_in
Sh_d
Sh_e “ R ” L
>
wr_en
OUT
Final Architecture
KeyReg 56 ’ b
Register 32
b input IP - 1
wiring PC 2
Wiring
>48
Text 64
Expand S
Box
512 x 4 P
>32
PC (wiring)
b Latch
2:1
mux
Sub_rnd
txt_in
ready
key_in “ R ” L 48
wr_en
OUT
2:1mux
Enc_ShiftL
Dec_ShiftR
Sh_d
Sh_e
Initial Architecture
Key2 56 ’ b
SRAM
Barrel
Shifter I:
0,0,1,1,1,1,1,1,0,1,1,1,1,1,1,0 PC - 2
(wiring)
Key set
Current
and next
keys
2 x 48
Register 48 32 1
XOR
Expansion
b 48
Plaintext 64
R[I]
L[I] S
box
8x4x16x4
ROM
L[I 1]
R[I
b Register P
Key1,3
b output
b input
demux 16
b ROM IP
mux 2 nd
Architecture Revision
KeyReg 56 ’ b
Register 32
b input
Enc_ShiftL
Dec_ShiftR IP - 1
wiring PC
Wiring
>48
Text 64
Expand S
Box
512 x 4 P
>32
PC (wiring)
b Latch
2:1
mux
Sub_rnd
e/d
txt_in
ready
key_in
Sh_d
Sh_e “ R ” L 48
wr_en
OUT
2:1mux
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14. Floorplan Evolution
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15. Right Barrel Shifter 56’b
Revised Floorplan
Total Area:
um2 = 0.112mm2
Transistor Density: trans/ um2
269 um
PC (wiring) 64 -> 56
64’b 2:1 demux
56’b Key Latch
56’b 2:1 mux
KeySub 56’b Register
Enc_ShiftL
32’b 2:1 demux
64’b 2:1 mux
IP (wiring)
Data Reg (L) 32’b
IP-1 Wiring
Expand
48’b XOR
PC-2 wiring 56b -> 48b
S-box 512 x 4’b
P Wiring
32’b XOR
Program Control
(Instruction ROM)
Input
Output
Dec_ShiftL
Data Reg (R) 32’b
32’b 2:1 mux
415 um
Almost Final Floorplan
32’b Latch
PC1
Right Barrel Shifter 56’b
Mux
56’b Key Reg
PC2 IP
IP-1
32’b Text Register (L)
32’b Text Register (R)
32’b Mux
32’b XOR
Expand
48’b XOR P
All large functional blocks use Metal 1 and Metal 2. M1 M2 M3 M4
Input
Output
Program Control
clock
379μm
367μm
Left Barrel Shifter 56’b
Original Floorplan
PC (wiring)
64 -> 56
64’b 2:1 demux
56’b Key Latch
56’b 2:1 mux
KeySub 56’b Register
Des_ShiftR
Enc_ShiftL
32’b 2:1 demux
64’b 2:1 mux
IP (wiring)
Text 64’b Reg
IP-1 Wiring
Expand
48’b XOR
PC-2 wiring 56b -> 48b
S-box 512 x 4’b
P Wiring
32’b XOR
Program Control
(Instruction ROM)
Input
Output um um
64’b
2:1 mux
125,534 um2 =
.126 mm2
Density
.09 Trans/um2
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16. Final Floorplan
OUTPUT
INPUT
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17. Encryption Transaction Verification
Input : Credit Information
Credit #:
Security code: 319
Input Pin # : 4510
key1: 0x32, 0x37, 0x33, 0x39, 0x38, 0x32, 0x30, 0x31
key2: 0x34, 0x38, 0x35, 0x36, 0x32, 0x33, 0x38, 0x39
key3: 0x33, 0x31, 0x39, 0x34, 0x35, 0x31, 0x30, 0xFF
Expiration Date: 08/2008
Plain Text : 0x30, 0x38, 0x2F, 0x32, 0x30, 0x30, 0x38, 0xFF
Output : Cipher Text
0x2F, 0x81, 0xA8, 0xBF, 0x3C, 0x6B, 0xDF, 0xB4
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18. Structural Verification Behavioral Verification
Expected Output :
2f 81 a8 bf 3c 6b df b4
Verification
Verify
C Simulation
Behavioral
Structural
C code Verification
Structural Verification
Behavioral Verification
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19. Schematic Verilog Verification
Encryption
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20. Chip Spice Verification
Encryption
Propagation Time:
908ps
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21. Chip Spice Verification
Encryption
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22. Schematic Verilog Verification
Decryption
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23. Chip Spice Verification
Decryption
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24. Layout All simple Components built to same height
6.48μm rail to rail height
Transistors enlarged to capacity of cell height
Simple components use Metals 1 and 2
Global routing over modules in Metals 3 and 4
Exclusive OR
Enable / Reset asserted high D Flip Flop
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25. Layer Masks Metal 1 Metal 2 Metal 3 Metal 4 Poly/Active 18-525
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26. Full Chip Layout 13,697 Transistors 366.8μm x 378.8 μm
Key Register
Final Permutation
Initial Permutation
Inverse Permutation
Text Register
Expand Permutation
P Permutation
XOR
SBOX ROM and Decoders
Input Latch
Barrel Shifters
PC2 Permutation
Program
Control
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27. Left Barrel Shifter 392 Transistors 3696.1 um2
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28. Program Control 926 Transistors 9003.3 um2 0.10285 transistors/um2
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29. PC1 Permutation 240 Transistors 10825.03um2 0.02217 transistors/um2
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30. 64’b Text Register 1536 Transistors 7864.56um2 0.1953 transistors/um2
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31. SBOX1 ROM and Decoder 592 Transistors 2357.3um2
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32. Layout Optimizations Compacting of Permutation Wiring Area Savings
Switch to lower metal layers
Chop wiring to minimal length
Compact wire placement
Area Savings
60% reduction in area for PC1
50 – 60% area reduction over all permutations
13.1um
31.5um
PC1 Permutation
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33. Chip Pinouts Signal Direction Assert/ Width Description
Control Signals
CLK
Input
Rise
Global Clock
RST
High
Global Reset
EN/DE
Encryption Mode
Low
Decryption Mode
Data I/O
Din 32
Input Data/Key
Dout
Output
Output Cipher Text RD
Output Ready GK
Get Next Key
Power Signals
Vdd
Power Supply
Gnd
Ground
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34. Chip Specification (I)
Required Inputs:
32 bits data input at pins
1 bit reset at pin
1 bit encryption/decryption mode control at pin
1 bit clock at pin
1 bit Vdd at pin
1 bit Gnd at pin
Provided Output :
32 bits cipher data output at pins
1 bit ready at pin
Total Pin Count : 71
1 bit get next key at pin
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35. Chip Specifications (II)
Total Pin Count:
Chip Size: μm x μm
Chip Area: μm2
Chip Aspect Ratio: 1:1.03
Transistor Count: ,697 (PMOS: 4,324 NMOS: 9,373)
Transistor Density: transistors/μm2
μm2/transistor
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36. Chip Specifications (III)
Core Voltage: 1.8V
Clock Speed: 300MHz
Operation: 256’b Input ’b Output
Over 54 clock cycles
Data Throughput: 343 Mbits / second
64bits / 54 clocks 300MHz = 343Mbps
343Mbits/sec > Current network connection speeds: 100Mbits/sec
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37. Module Specifications
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38. Module Transistors Latch (8%) 6 bit Adder (1%) Mux (10%) ROM (40%)
Barrel Shifter (6%)
Register (21%)
XOR (5%)
Permutation (9%)
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39. Module Areas Latch (3%) 6 bit Adder (1%) Mux (7%) ROM (18%)
Barrel Shifter (6%)
Register (12%)
XOR (3%)
Permutation (50%)
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40. Module Transistor Densities
Adder
Latch
Mux
Adder
Barrel Shifter
ROM
ROM
Permutation
Register
XOR
Register
Permutation
XOR
Barrel Shifter
Mux
Latch
Module Transistor Densities
Module Areas
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41. Issues Encountered Floorplan Spice Simulation (Not Trivial !!!)
Interconnections between components back and forth due to complicated algorithm
Spice Simulation (Not Trivial !!!)
Simulation never fails at the critical path
Vdd Strength drops along conductor wires
Solutions
Increase thickness of Vdd
Add more Vdd connections
Nwell contacts on Vdd! lines improved PCROM simulation
Buffer weak ROM input signals
Improve rise/fall times of 48-bit XOR and ROM
Add M1_P to Ground contacts throughout ROMs
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42. Vdd! Degradation Control Signal ROM
Actual lengths from top level design
Simulation of Program Control and ROM using
vdd! and gnd! wiring from top-level
Outputs all very low (400mV)
400mV
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43. Vdd! Degradation Control Signal ROM
Additional M1_P contacts added to ROM
Simulation of Program Control and ROM using
vdd! and gnd! wiring from top-level
Outputs all very low (400mV)
400mV
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44. Vdd! Degradation Control Signal ROM
Doubling the wiring should halve the resistance
Simulation of Program Control and ROM
using twice the wiring
Output correct with maximum value of 1.5 volts
1.5 volts
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45. Conclusion
Implementation of Triple DES Encryption/Decryption for both host and client ends using 0.18μ CMOS technology
Maximum clock frequency of 300MHz with maximum throughput of 343Mbits / second
Chip area of 366.8μm x 378.8μm with aspect ratio of 1:1.03
Attains speeds appropriate for application in Automated Teller Machines (200+ MHz)
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