1. Modern processor design

2. Engineering design

3. The dynamic-static interface (DSI)

4. Conceptuall illustration of possible placement of DSI in ISA design

5. Performance simulation metods
Trace-driven simulation
Execution-driven simulation

6. Scalar pipeline machine

7. Superpipelined machine of degree m=3

8. Superpipelined MIPS R4000
8-stage pipeline

9. Superscalar machine of degree n=3

10. VLIW machine of degree n=3

11. Pipeline example
4-stage
11-stage

12. Two commercial instruction pipelines

13. Activity of pipeline stages

14. 6-stage instruction pipeline

15. I-cache and D-cache

16. Access to RF

17. RAW, WAR, and WAW data dependencies

18. WAW, WAR, and RAW hazards

19. Forwarding paths

20. Forwarding paths for ALU leading instructions

21. Forwarding paths for Load leading instructions

22. Impact on ALU, Load, and Branch penalties with increasing pipeline depth

23. Mitigating the Branch penalty impact of deep pipelines

24. Direct, associative, and set-associative caches

25. Strategy of cache design

26. Memory hierarchy

27. Main memory and I/O

28. DRAM accesses

29. Virtual to physical address translation

30. Processes switching

31. Paging tables

32. Direct cache

33. Associative cache

34. Set-associative cache

35. Virtual to physical address translation

36. Disk

37. I/O device communication

38. Stall cycle induced by backward propagation of stalling

39. Machine parallelism

40. Parallel pipeline of width s=3

41. Parallel pipeline - examples
5-stage Pentium parallel pipeline s=2
5-stage i486

42. Parallel pipeline with four execution pipes

43. The Motorola 88110 superscalar microprocessor

44. Interpipeline-stage buffers multi-entry buffer with reordering
single-entry buffer
multi-entry buffer
multi-entry buffer with reordering

45. Dynamic pipeline of width s=3

46. 6-stage superscalar pipeline

47. Instruction dispatching in superscalar pipeline

48. Centralized reservation station

49. Distributed reservation stations

50. Dynamic pipeline with reservation stations and reorder buffer

51. Disruption of sequential control flow by Branch instructions

52. Branch target address generation penalties

53. Branch condition resolution penalties

54. Alpha pipeline stages

55. HP PA 7100 pipeline stages

56. IBM POWER (RIOS) pipeline stages

57. Intel i960CA pipeline stages

58. Intel Pentium pipeline stages

59. Cyrix 6x86 pipeline stages

60. Intel P6 pipeline stages

61. MIPS R10000 pipeline stages

62. Motorola MC68060 pipeline stages

63. IBM/Motorola PowerPC 604 pipeline stages

64. Sun UltraSPARC-I pipeline stages