1. MIPS Pipeline and Branch Prediction Implementation Shuai Chang

2. Project Overview ECE 369 Project Single Cycle Datapath ◦ Easy to implement ◦ Poor performance Performance Consideration ◦ Resource utilization ◦ Pipeline implementation ◦ Pipeline + Branch prediction

3. Original Design

4. Methodology Implemented in Verilog HDL Simulation ◦ Xilinx ISE 13.2 Hardware ◦ Xilinx Spartan 3E FPGA Devlopment Board

5. Methodology Implementation ◦ Pipeline ◦ Branch prediction

6. Methodology Inputs ◦ 2 files: Assembly Program and Data file 32 * 32 Frame 16 * 16 Window X = 0, Y = 8, SAD (Sum of Absolute Difference) = 0 is expected to be returned

7. Assembly Program Executed

8. Methodology Outputs ◦ Returned X, Y ◦ SAD ◦ Execution Time = CycleCount * CriticalPathDelay

9. Results

10. Start Earlier? Support more instructions Optimize logic Cache implementation

11. Questions?