1. 1 Seoul National University Pipelining Basics

2. 2 Sequential Processing Seoul National University

3. 3 Pipelined Processing Seoul National University

4. 4 Basic Steps of Execution Seoul National University 1. Instruction fetch step ( F ) 2. Instruction decode/register fetch step ( D ) 3. Execution/effective address step ( E ) 4. Memory access (M) 5. Register write-back step (W)

5. 5 Pipelined Instruction Execution Seoul National University Sequential Execution Pipelined Execution addl %ecx, %eax subl %edx, %ebx andl %edx, %ecx

6. 6 Basic Pipeline Seoul National University Clock number Instruction number 123456789 Instruction i FDEMW Instruction i + 1 FDEMW Instruction i + 2 FDEMW Instruction i + 3 FDEMW Instruction i + 4 FDEMW

7. 7 Major Hurdles of Pipelining Seoul National University Structural Hazard Data Hazard Control Hazard

8. 8 Structural Hazard Seoul National University FDEMW FDEMW FDEMW FDEMW Clock number Instruction number 123456789 Load Instruction FDEMW Instruction i + 1 FDEMW Instruction i + 2 FDEMW Instruction i + 3 FDEMW Instruction i + 4 FDEMW

9. 9 Solutions to Structural Hazard Seoul National University Resource Duplication  example  Separate I and D caches for memory access conflict  Multi-port register file for register file access conflict

10. 10 Data Hazard (RAW hazard) Seoul National University FME FME Time addl %edx, %eax subl %eax, %ecx W WD D

11. 11 Solutions to Data Hazard Seoul National University Freezing the pipeline (Internal) Forwarding Compiler scheduling

12. 12 Freezing The Pipeline Seoul National University ALU result to next instruction Load result to next instruction FME addl %edx, %eax subl %eax, %ecx stall mrmovl 0(%edx), %eax addl %edx, %eax W stallFD D FME W FD D

13. 13 (Internal) Forwarding Seoul National University ALU result to next instruction (Stall X) Load result to next instruction (Stall 1) FME addl %edx, %eax subl %eax, %ecx FME mrmovl 0(%edx), %eax addl %edx, %eax FME stallFME Load interlock D D W W DW D

14. 14 Control Hazard Seoul National University Caused by PC-changing instructions ((conditional/unconditional) Jump, Call/Return) For 5-stage pipeline, 3 cycle penalty 15% branch frequency. CPI = 1.45 Branch Instruction FDEMW Branch successor F stall FDEMW Branch successor + 1 FDEMW Branch successor + 2 FDEM Branch successor + 3 FDE Branch successor + 4 FD Branch successor + 5 F (Example)

15. 15 Branch Prediction Seoul National University Predict-taken Taken branch instructionFDEMW Branch targetFDEMW Branch target + 1FDEMW Branch target + 2FDEMW Branch target + 3FDEMW Untaken branch instructionFDEMW Branch targetFDEidle Branch target + 1FDidle Branch target + 2Fidle Untaken branch instruction + 1FDEMW ~60% success rate