151. Sequential Circuits Design Problem: Combinational Lock
Detect the lock sequence 3-1-2

152. Storage Elements: Latches vs. Flip Flops
Latch: level sensitive: continuously sampling input while level is high
Flip Flop: sample input at a transition of the clock
positive edge triggered, negative edge triggered D
Clk
Qlatch
Qff(neg edge)

153. S-R Latch (Active High)
S R Q
0 0
0 1
1 0
1 1
R(reset)
S(set) Q S R Q

154. S-R Latch (Active Low)
S R Q
0 0
0 1
1 0
1 1
R(reset) Q Q
S(set) S R Q

155. Controlled S-R Latch S(set) Q Clock Q R(reset) C S R Q 0 X X 1 0 0
1 0 0
1 0 1
1 1 0
1 1 1

156. D Latch D Q
Clock Q
C D Q
0 X
1 0
1 1

157. Flip Flops
Problem: latches are sensitive to any changes that occur with the input while the clock or control signal is high
Glitches/Hazards
Unsynchronized changes
Solution use flip-flops, devices that react only on the clock edge

158. Master-Slave D Flip FlopY D
D Q
D latch
(Master) C
D Q
D latch
(Slave) C Q
Clock D
Clk Y Q

159. Master-Slave J-K Flip Flop
S Q
S-R latch
(Master)
R C
D Q
D latch
(Slave)
C Q Q J Y K
Clock
Clk J K Y Q

160. Flip Flop Descriptions
Several ways to describe a Flip Flop
Example: Toggle Flip Flop:
Inverts output when input is true
Characteristic tables:
How does the FF respond to its inputs
Determines how to design the element
Excitation tables:
How do you get a result out of a FF
Determines how to use the element
T Q
Toggle
Flip Flop C
T Q(t) Q(t+1)
0 0 0
0 1 1
1 0 1
1 1 0
Q(t) Q(t+1) T
0 0
0 1
1 0
1 1

161. Flip Flop Descriptions (cont.)
S-R Flip Flop:
D Flip Flop: S R Q ( t ) Q ( t + 1 ) Q ( t ) Q (
t+1 ) S R 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 D Q ( t ) Q ( t + 1 ) Q ( t ) Q (
t+1 ) D 1 1 1 1 1 1 1 1

162. Flip Flop Descriptions (cont.)
J-K Flip Flop J K Q ( t ) Q ( t + 1 ) Q ( t ) Q (
t+1 ) J K 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

163. Design Example
Design a D Flip Flop with an SR Flip Flop

164. Design Example
Design a T Flip Flop with a JK Flip Flop

165. (combinational logic)
Finite State Machines
Need to implement circuits that remember history
Traffic Light controller, Sequence Lock, ...
History will be held in flip flops
Seqential Logic needs more complex design steps
State Diagram to describe behavior
State Table to specify functions (like Truth Table)
Implementation of combinational logic as controller
Controller
(combinational logic)
FFs
Inputs
Outputs
Next State
Previous
(Current)
State

166. Finite State Machine Example
Example: Odd Parity Checker
Assert output whenever input bit stream has odd # of 1's
Reset
0/0
Even
1/0
1/1
Odd
0/1
State
Diagram
Even: State = 0, Odd: State = 1

167. Finite State Machine Example (cont.)
NS = PS xor PI; OUT = PS xor PI PS NS
Output
Input D Q
CLK Q R
\Reset
Input 1 1 1 1 1 1 1
Clk
Output

168. State Diagrams Graphical diagram of FSM behavior
States represented by circles
Transitions (actions) represented by arrows connecting states
Labels on Transitions give cause of action, resulting output
Inputs causing transition/Outputs
Note: We cover Mealy machines here; Moore machines put outputs on states, not transitions
Finite State Machine: State Diagram with finite number of states
Reset
0/0
Even
1/0
1/1
Odd
0/1

169. State Diagram Example
Circuit that cycles through Gray code when input true, holds value otherwise
Gray code: Code on top of K-Map

170. State Table
“Truth table” for sequential circuits

171. State Table Example
State Table for Gray code circuit

172. FSM Design Process 1. Understand the problem 2. Draw the state diagram
3. Use state diagram to produce state table
4. Choose which type of Flip Flops to use
5. Implement the combinational control logic

173. Vending Machine Example
Deliver package of gum after >= 15 cents deposited
Single coin slot for dimes, nickels
No change returned
State Diagram: N
Coin
Vending
Open
Gum
Sensor D
Machine
Release
FSM
Mechanism
Reset
Clk

174. Vending Machine Example (cont.)
State Table:

175. Vending Machine Example (cont.)
Implementation: