Presentation is loading. Please wait.

Presentation is loading. Please wait.

CEC 220 Digital Circuit Design Sequence Detector Design Wednesday, April 01 CEC 220 Digital Circuit Design Slide 1 of 11.

Published byJade Warren Modified over 9 years ago

Similar presentations

Presentation on theme: "CEC 220 Digital Circuit Design Sequence Detector Design Wednesday, April 01 CEC 220 Digital Circuit Design Slide 1 of 11."— Presentation transcript:

1 CEC 220 Digital Circuit Design Sequence Detector Design Wednesday, April 01 CEC 220 Digital Circuit Design Slide 1 of 11

2 Lecture Outline Wednesday, April 01 CEC 220 Digital Circuit Design More Sophisticated Sequence Detector Design Incompletely Specified State Graph Boolean State Graph Notation Slide 2 of 11

3 Sequence Detector Design More Sophisticated Sequence Detector Wednesday, April 01 CEC 220 Digital Circuit Design Develop a sequence detector which asserts its output (Z) if either a “010” or “1001” is detected on the serial input (X)  How should the state machine respond to  X= 0,0,1,0,1,0,0,1,0,0,1,…  Z=  Develop the state graph for a Moore machine solution  Develop the state graph for a Mealy machine solution 0,0,0,1,0,1,1,0,1 Slide 3 of 11

4 Incompletely Specified State Graphs Wednesday, April 01 CEC 220 Digital Circuit Design Design a Vending Machine  Dispense a stick of gum when 15 ¢ or more is collected and then return to “start”  Accept a single nickel or dime at a time  No change is provided BLOCK DIAGRAM Example behavior: N: 0,1,0,0,0,0,… D: 0,0,1,0,1,1,… Assumption: System clock is “high speed” Assumption: System clock is “high speed” Coin Sensor Vending Machine Gum Dispenser N D Z ClkReset Z: 0,0,1,0,0,1,… Slide 4 of 11

5 Incompletely Specified State Graphs Wednesday, April 01 CEC 220 Digital Circuit Design State Graph  Moore Machine 00 State Name Output Legend : Input=ND S 0¢ 0 RESET S5 ¢ 0 10 S10 ¢ 0 10 S15 ¢ 1 01 00 00, 01, 10 01 Present State Next StatePresent Output (Z) ND=00ND=01ND=10ND=11 S 0¢ S 5¢ S1 0¢ S 15¢ Present State Next StatePresent Output (Z) ND=00ND=01ND=10ND=11 S 0¢ 0 S 5¢ 0 S1 0¢ 0 S 15¢ 1 Present State Next StatePresent Output (Z) ND=00ND=01ND=10ND=11 S 0¢ S1 0¢ S 5¢ X 0 S1 5¢ S 10¢ X 0 S1 5¢ X 0 S0 ¢ X 1, 01 The state graph is incompletely specified!! The state graph is incompletely specified!! Slide 5 of 11

6 Incompletely Specified State Graphs Wednesday, April 01 CEC 220 Digital Circuit Design Circuit design (D-type flip-flops) Present State Next StatePresent Output (Z) Flip-Flop Inputs (D A D B ) 0001101100011011 S 0¢ S1 0¢ S 5¢ X0 S1 5¢ S 10¢ X0 S1 5¢ X0 S0 ¢ X1 QAQBQAQB S 0¢ = 00 S 5¢ = 01 S1 0¢ = 10 S15 ¢ =11 State Encodings Present Output (Z) Flip-Flop Inputs (D A D B ) 0001101100011011 00 1001XX0 01 1110XX0 10 11 XX0 1100 XX1 Present Output (Z) Flip-Flop Inputs (D A D B ) 0001101100011011 00 1001XX0001001XX 01 1110XX0011110XX 10 11 XX01011 XX 1100 XX100 XX 00011110 0001X0 0101X1 1100X0 1011X1 00011110 0000X1 0111X0 1100X0 1001X1 Slide 6 of 11

7 Incompletely Specified State Graphs Wednesday, April 01 CEC 220 Digital Circuit Design State Graph  Mealy Machine 00/0 State Name Legend : Input / Output (ND) S 0¢ RESET S5 ¢ 10 /0 S10 ¢ 10 /0 10/1 00/0 01/0 Present State Next StatePresent Output (Z) 0001101100011011 S 0¢ S 5¢ S1 0¢ The state graph is incompletely specified!! The state graph is incompletely specified!! 01/1 Present State Next StatePresent Output (Z) 0001101100011011 S 0¢ 000X S 5¢ 010X S1 0¢ 011X Present State Next StatePresent Output (Z) 0001101100011011 S 0¢ S1 0¢ S 5¢ X000X S 0¢ S1 0¢ X010X S 0¢ X011X Slide 7 of 11

8 Incompletely Specified State Graphs Wednesday, April 01 CEC 220 Digital Circuit Design Circuit design (D-type flip-flops) QAQBQAQB S 0¢ = 00 S 5¢ = 01 S1 0¢ =10 State Encodings 00011110 0001X0 0100X1 11XXXX 1010X0 00011110 0000X1 0110X0 11XXXX 1000X0 Present State Next StatePresent Output (Z)Flip-Flop In (D A D B ) 0001101100011011 00011011 S 0¢ S1 0¢ S 5¢ X000X S 0¢ S1 0¢ X010X S 0¢ X011X Present State Next StatePresent Output (Z)Flip-Flop In (D A D B ) 0001101100011011 00011011 00 1001XX000X 01 0010XX010X 10 00 XX011X 11XX Present State Next StatePresent Output (Z)Flip-Flop In (D A D B ) 0001101100011011 00011011 00 1001XX000X001001XX 01 0010XX010X010010XX 10 00 XX011X1000 XX 11XX XXXX 00011110 0000X0 0101X0 11XXXX 1001X1 Slide 8 of 11

9 Boolean State Graph Notation Wednesday, April 01 CEC 220 Digital Circuit Design Recall the Moore Machine Chart 00 State Name Output Legend : Input=ND S 0¢ 0 RESET S5 ¢ 0 10 S10 ¢ 0 10 S15 ¢ 1 01 00 00, 01, 10, 01 NDND RESET S15 ¢ Z Boolean State Graph Notation Slide 9 of 11

10 Boolean State Graph Notation Wednesday, April 01 CEC 220 Digital Circuit Design Recall the Mealy Machine Chart 00/0 S 0¢ RESET S5 ¢ 10 /0 S10 ¢ 10 /0 10/1 00/0 01/0 01/1 State Name Legend : Input / Output (ND) (Z) S 0¢ S5 ¢ S10 ¢ RESET N  D/Z Slide 10 of 11

11 Next Lecture Wednesday, April 01 CEC 220 Digital Circuit Design More FSM Examples Slide 11 of 11

Download ppt "CEC 220 Digital Circuit Design Sequence Detector Design Wednesday, April 01 CEC 220 Digital Circuit Design Slide 1 of 11."

Similar presentations

ENGIN112 L23: Finite State Machine Design Procedure October 27, 2003 ENGIN 112 Intro to Electrical and Computer Engineering Lecture 23 Finite State Machine.

ENGIN112 L23: Finite State Machine Design Procedure October 27, 2003 ENGIN 112 Intro to Electrical and Computer Engineering Lecture 23 Finite State Machine.
Some Slides from: U.C. Berkeley, U.C. Berkeley, Alan Mishchenko, Alan Mishchenko, Mike Miller, Mike Miller, Gaetano Borriello Gaetano Borriello Introduction.

Some Slides from: U.C. Berkeley, U.C. Berkeley, Alan Mishchenko, Alan Mishchenko, Mike Miller, Mike Miller, Gaetano Borriello Gaetano Borriello Introduction.
CS1Q Computer Systems Lecture 12 Simon Gay. Lecture 12CS1Q Computer Systems - Simon Gay 2 Design of Sequential Circuits The systematic design of sequential.

CS1Q Computer Systems Lecture 12 Simon Gay. Lecture 12CS1Q Computer Systems - Simon Gay 2 Design of Sequential Circuits The systematic design of sequential.
TOPIC : Finite State Machine(FSM) and Flow Tables UNIT 1 : Modeling Module 1.4 : Modeling Sequential circuits.

TOPIC : Finite State Machine(FSM) and Flow Tables UNIT 1 : Modeling Module 1.4 : Modeling Sequential circuits.
Circuits require memory to store intermediate data

Circuits require memory to store intermediate data
Unit 13 Analysis of Clocked Sequential Circuits Ku-Yaw Chang Assistant Professor, Department of Computer Science and Information.

Unit 13 Analysis of Clocked Sequential Circuits Ku-Yaw Chang Assistant Professor, Department of Computer Science and Information.
Sequential Circuit Design

Sequential Circuit Design
ECE 331 – Digital System Design Introduction to and Analysis of Sequential Logic Circuits (Lecture #20) The slides included herein were taken from the.

ECE 331 – Digital System Design Introduction to and Analysis of Sequential Logic Circuits (Lecture #20) The slides included herein were taken from the.
ECE 331 – Digital System Design

ECE 331 – Digital System Design
6/12/20151 Sequence Detectors Lecture Notes – Lab 4 Sequence detection is the act of recognizing a predefined series of inputs A sequence detector is a.

6/12/20151 Sequence Detectors Lecture Notes – Lab 4 Sequence detection is the act of recognizing a predefined series of inputs A sequence detector is a.
ECE C03 Lecture 101 Lecture 10 Finite State Machine Design Hai Zhou ECE 303 Advanced Digital Design Spring 2002.

ECE C03 Lecture 101 Lecture 10 Finite State Machine Design Hai Zhou ECE 303 Advanced Digital Design Spring 2002.
Give qualifications of instructors: DAP

Give qualifications of instructors: DAP
Contemporary Logic Design Finite State Machine Design © R.H. Katz Transparency No. 14-1 Chapter #8: Finite State Machine Design 8.1 - 8.2 Finite State.

Contemporary Logic Design Finite State Machine Design © R.H. Katz Transparency No Chapter #8: Finite State Machine Design Finite State.
Sequential Circuit Design

Sequential Circuit Design
ECE C03 Lecture 121 Lecture 12 Finite State Machine Design Prith Banerjee ECE C03 Advanced Digital Design Spring 1998.

ECE C03 Lecture 121 Lecture 12 Finite State Machine Design Prith Banerjee ECE C03 Advanced Digital Design Spring 1998.
3/13/20081 Lab 6 Solution Part 1: Design a sequence detector for the sequence “00101” Part 2: a b See sm1.vhdSee sm2.vhd See seq1.vhd.

3/13/20081 Lab 6 Solution Part 1: Design a sequence detector for the sequence “00101” Part 2: a b See sm1.vhdSee sm2.vhd See seq1.vhd.
1 Synchronous Sequential Circuit Design. 2 Sequential circuit design In sequential circuit design, we turn some description into a working circuit – We.

1 Synchronous Sequential Circuit Design. 2 Sequential circuit design In sequential circuit design, we turn some description into a working circuit – We.
ECE 301 – Digital Electronics

ECE 301 – Digital Electronics
ECE 301 – Digital Electronics Introduction to Sequential Logic Circuits (aka. Finite State Machines) and FSM Analysis (Lecture #17)

ECE 301 – Digital Electronics Introduction to Sequential Logic Circuits (aka. Finite State Machines) and FSM Analysis (Lecture #17)
ECE 331 – Digital Systems Design Introduction to Sequential Logic Circuits (aka. Finite State Machines) and FSM Analysis (Lecture #19)

ECE 331 – Digital Systems Design Introduction to Sequential Logic Circuits (aka. Finite State Machines) and FSM Analysis (Lecture #19)

Similar presentations

Ads by Google