1. 09/02/20121 Delay Chip Prototype & SPI interface Joan Mauricio La Salle (URL) 15/02/2013

2. 15/02/20132 Delay Chip Overview SPI Slave Reset Block Mux VCDL+Mux Phase Comp + Charge Pump Config Status VCDL+Mux Config rstnRst coarse vControl clkRef clkINT clkT&H clkADC vControl Analog Config Digital Config LVDS Clock CMOS Clock Slow Control !en, clk din, dout nRst

3. 15/02/20133 Delay Chip Features –SPI Slave interfaces with the SPI Master and generates: –Register Select. –Read / !Write. –Serial Registers: –16 Bits RW (Config. Registers). –8 Bits RO (Status Registers). –4 DLL Channels: –1 Phase Comparator + Charge Pump per Channel. –2 Config. + 1 Status Register per Channel. –3 independent LVDS Clk outputs per Channel.  24 pads!!!

4. 15/02/20134 Slow Control – SPI Slave –SPI Modes: –We are currently implementing Mode 1. ModeCPOLCPHA 000 101 210 311

5. 14/01/20135 Slow Control – SPI Slave State Machine –SEU tolerant State Machine: –Hamming distance between Idle and critical states is 2. Idle state  spiEn = ‘0’ If 1-bit SEU occurs: E 100, E 100, E 111  E 101 Pump Rst Addr Dec Reg Selection Not in Idle state afeter reset!!!!

6. 15/02/20136 Slow Control – SPI Slave Features –SPI Mode 1. –No ‘dead’ cycles between Addresses and Data. –Up to 64 Selectable Registers (32 Config. + 32 Status):  Only 8 Config. + 4 Status used in this chip. –SDI / SDO Bypass for troubleshooting purposes. –Charge Pumps can be reset via software. –SEU tolerant. –Area = 340x73 um 2.

7. 15/02/20137 Slow Control – SPI Addresses ADDRICECAL ChWidthDescription 0x00016INT / T&H Clk Conf. 0x01016ADC Clk Conf. 0x02116INT / T&H Clk Conf. 0x03116ADC Clk Conf. ··· 0x10216INT / T&H Clk Conf. 0x11216ADC Clk Conf. 0x12316INT / T&H Clk Conf. 0x13316ADC Clk Conf. ··· 0x40Any-Charge Pump Reset ··· 0xA008Status Reg. 0xA118Status Reg. 0xB028Status Reg. 0xB138Status Reg. ··· 0xFF--SDI / SDO Bypass R/!WPump RstStatus/!ConfRSEL 4 RSEL 3 RSEL 2 RSEL 1 RSEL 0

8. 15/02/20138 Slow Control – Configuration Registers (16b) –RW Registers. –No state machine is required. –16 Bits. –Signals: –Preset (Hardware) –Register Select –R/!W –Serial Clock –Serial Data Input –Serial Data Output (tristated)

9. 15/02/20139 Slow Control – Status Registers (8b) –RO status bits (no memory). –No state machine is required. –8 Bits. –Signals: –Register Select –Serial Clock –Serial Data Output (tristated)

10. 15/02/201310 Slow Control – Conf. Reg. Write Simulation 110 1 000 1 100000 1 00000000 1 1 0 0 1 1 0 1 0 0 0 1 1 0 0 0 1 –Write = 0x9A31.

11. 15/02/201311 Slow Control – Conf. Reg. Read Simulation 100000 1 00000000 1 1 0 0 1 1 0 1 0 0 0 1 1 0 0 0 1 –Read = 0x9A31.

12. 15/02/201312 Slow Control – Status Reg. Read Simulation 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 01 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 1 0 0 0 1 –Read = 0xD1.

13. 15/02/201313 Delay Chip Prototype –Next Run @ 13/03/2013 – Europractice. –New test board (Analog Mezzanine) is being designed. –Some changes needed in the FEB FPGA: –SPI Master capability (opencores.org). –Interface between CAT and SPI block. –4 Pins needed (5 if the board has two SPI Slaves).