1. 09/02/20121 Delay Chip Prototype & Delay Chip Test Board Joan Mauricio – Xavier Ondoño La Salle (URL) 12/04/2013

2. 12/04/20132 Delay Chip Overview SPI Slave Reset Block Mux VCDL+Mux Phase Comp + Charge Pump Config Status VCDL+Mux Config rst nRst coarse vControl clkRef clkINT clkT&H clkADC vControl Analog Config. Digital Config. Diff. LVDS Clock Diff.CMOS Clock Slow Control !en, clk din, dout nRst powRstIn powRstOut (externally shorted) vRef ···

3. 12/04/20133 Delay Chip Features (1/3) –QFN48 Package. –4 DLL Channels (12 sub-channels). –Jitter: 4 ps. –DNL: 18 ps. –Delay Range: 17.45 ~ 39.88 ns. –~280 mW power consumption. –70 mW per DLL Channel. –INT/T&H DLL: 27 mW. –ADC DLL: 13 mW. –3 LVDS Drivers: 30 mW.

4. 12/04/20134 Delay Chip Features (2/3) –Each DLL channel contains: –1 x LVDS to CMOS driver. –2 x VCDLs. –3 x Multiplexors. –1 x Phase Comparator. –1 x Charge Pump. –2 x Configuration Registers. –1 x Status Register –3 x CMOS to LVDS driver.

5. 12/04/20135 Delay Chip Features (3/3) –SPI Slave: –Interfaces with SPI Master (Mode 1). –Works fine @ 20 Mbps. –Up to 32 Configuration registers and 32 Status Registers. –Also implements a software reset (used to clear the charge pumps). –Serial Registers: –16 Bits R/W TMR Registers (Configuration). –8 Bits RO (Status). No memory. –Reset: –Power Reset signal (1-ms-wide, active high) is generated. –Power Reset can be inhibited by not shorting pins 47 and 48. –Glitch supressor ensures that SETs do not accidentally reset the chip (up to 8-ns-wide glitch).

6. 12/04/20136 Power Reset & Glitch Supressor

7. 12/04/20137 SPI Slave Addressing Scheme ADDRICECAL ChWidth (bits)Description 0x00016Integrator / Track&Hold Clock Configuration Register. 0x01016ADC Clock Configuration Register. 0x02116Integrator / Track&Hold Clock Configuration Register. 0x03116ADC Clock Configuration Register. ··· 0x10216Integrator / Track&Hold Clock Configuration Register. 0x11216ADC Clock Configuration Register. 0x12316Integrator / Track&Hold Clock Configuration Register. 0x13316ADC Clock Configuration Register. ··· 0x40Any-Software Reset of the Charge Pumps. ··· 0xA008Status Register. 0xA118Status Register. 0xB028Status Register. 0xB138Status Register. ··· 0xFF--SDI / SDO Bypass. For testing purposes. b7b7 b6b6 b5b5 b4b4 b3b3 b2b2 b1b1 b0b0 R/!WPump RstStatus/!ConfRSEL 4 RSEL 3 RSEL 2 RSEL 1 RSEL 0

8. –Integrator / Track & Hold Clock Configuration Registers (default 0x9E00): –ADC Clock Configuration Registers (default 0x9E00): –CE : LVDS Output Clock Enable. If 0, outputs are tri-stated (default = ‘1’). – ϕ T&H : Track & Hold Clock phase. MSB = b 13 (default = 0xF). – ϕ INT : Integrator Clock phase. MSB = b 8 (default = 0x0). – ϕ ADC : ADC Clock phase. MSB = b 13 (default = 0xF). –VCE : Enables Voltage Control monitors 0~3 (default = ‘0’). –DEB : Internal pads Output Enable (default = ‘0’). *Only available in SPI @ = 2. –LOCUS: LVDS Output Current Selector (default = ‘00’).  ‘00’: 3.0 mA.  ‘10’: 2.3 mA.  ’01’: 1.4 mA.  ‘11’:.35 mA. 12/04/20138 SPI Slave Configuration Data Frames b 15 b 14 b 13..9 b 8..4 b3b3 b2b2 b 1..0 CE- ϕ T&H ϕ INT VCEDEB*LOCUS b 15 b 14 b 13..9 b 8..4 b3b3 b2b2 b 1..0 CE- ϕ ADC ---LOCUS

9. –DLL Status Registers: –ESLOW : Error: VCDL is too slow. DNL > 0. –LOCKED : DLL is locked. –WFAST : Warning: VCNT i is near to cut VCDL NMOS transistors. 12/04/20139 SPI Slave Status Data Frame b7b7 b6b6 b5b5 b 4..0 ESLOWLOCKEDWFAST00000

10. TEST BOARD… 09/02/2012

11. –Main features: –Mechanically compatible with the analog mezzanine. –Clock signals will be tested with probes. –Requires 5 FPGA wires (2 SPI Masters). –It also can work in standalone mode (USB  SPI). –Coarse voltage: –Resistive Voltage Divider. –Low cost SPI DAC. 12/04/201311 Delay Chip Test Board Schematics

12. BACKUP… 09/02/2012

13. 12/04/201313 Delay Chip Pinout (1/3) CKT&H QFN-48 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 35 34 13141516171819202122 4443424140393837474645 SPIDINSPICLKSPIEN SPIDOUT V SS V DD CKINT CKT&H PWRSTOPWRSTIRSTCOARSEV SS V DD V SS CKT&H CKINT CKT&H CKINT VCNT V DD V SS VCNT CKINT CKT&H 12 2324 36 CKT&H 48 VCNT CKADC V SS V DD CLKREF CKADC CLKREF Control Voltages Power / Ground LVDS Clocks Slow Control (SPI)

14. 15/02/201314 Delay Chip Pinout (2/3) Pin No.MnemonicDescription 1CKADC Positive LVDS Clock Output pin to Channel 0 ADC. V CM = 1.2 V. V DIFF = 300 mV (r T = 100Ω). 2CKADC Negative LVDS Clock Output pin to Channel 0 ADC. V CM = 1.2 V. V DIFF = 300 mV (r T = 100Ω). 3CKADC Negative LVDS Clock Output pin to Channel 1 ADC. V CM = 1.2 V. V DIFF = 300 mV (r T = 100Ω). 4CKADC Positive LVDS Clock Output pin to Channel 1 ADC. V CM = 1.2 V. V DIFF = 300 mV (r T = 100Ω). 5CLKREFPositive LVDS Clock Input pin. V CM = 1.2 V. V DIFF = 400 mV (r T = 100Ω). 6V SS Ground. 7V DD Supply Voltage (3.3 V). 8CLKREFNegative LVDS Clock Input pin. V CM = 1.2 V. V DIFF = 400 mV (r T = 100Ω). 9CKADC Positive LVDS Clock Output pin to Channel 2 ADC. V CM = 1.2 V. V DIFF = 300 mV (r T = 100Ω). 10CKADC Negative LVDS Clock Output pin to Channel 2 ADC. V CM = 1.2 V. V DIFF = 300 mV (r T = 100Ω). 11CKADC Negative LVDS Clock Output pin to Channel 3 ADC. V CM = 1.2 V. V DIFF = 300 mV (r T = 100Ω). 12CKADC Positive LVDS Clock Output pin to Channel 3 ADC. V CM = 1.2 V. V DIFF = 300 mV (r T = 100Ω). 13SPIDINSPI Data Input. 14SPICLKSPI Clock. 15SPIENSPI Enable. Active low. 16SPIDOUTSPI Data Out. Open drain. 17VCNT DLL Channel 3 Control Voltage monitor. 18V SS Ground. 19V DD Supply Voltage (3.3 V). 20V DD Supply Voltage (3.3 V). 21CKINT Positive LVDS Clock Output pin to Channel 3 Integrator block. V CM = 1.2 V. V DIFF = 300 mV (r T = 100Ω). 22CKINT Negative LVDS Clock Output pin to Channel 3 Integrator block. V CM = 1.2 V. V DIFF = 300 mV (r T = 100Ω). 23CKT&H Positive LVDS Clock Output pin to Channel 3 Track & Hold block. V CM = 1.2 V. V DIFF = 300 mV (r T = 100Ω). 24CKT&H Negative LVDS Clock Output pin to Channel 3 Track & Hold block. V CM = 1.2 V. V DIFF = 300 mV (r T = 100Ω).

15. 15/02/201315 Delay Chip Pinout (3/3) Pin No.MnemonicDescription 25CKT&H Positive LVDS Clock Output pin to Channel 2 Track & Hold block. V CM = 1.2 V. V DIFF = 300 mV (r T = 100Ω). 26CKT&H Negative LVDS Clock Output pin to Channel 2 Track & Hold block. V CM = 1.2 V. V DIFF = 300 mV (r T = 100Ω). 27CKINT Positive LVDS Clock Output pin to Channel 2 Integrator block. V CM = 1.2 V. V DIFF = 300 mV (r T = 100Ω). 28CKINT Negative LVDS Clock Output pin to Channel 2 Integrator block. V CM = 1.2 V. V DIFF = 300 mV (r T = 100Ω). 29VCNT DLL Channel 2 Control Voltage monitor. 30V SS Ground. 31V DD Supply Voltage (3.3 V). 32VCNT DLL Channel 1 Control Voltage monitor. 33CKINT Negative LVDS Clock Output pin to Channel 1 Integrator block. V CM = 1.2 V. V DIFF = 300 mV (r T = 100Ω). 34CKINT Positive LVDS Clock Output pin to Channel 1 Integrator block. V CM = 1.2 V. V DIFF = 300 mV (r T = 100Ω). 35CKT&H Negative LVDS Clock Output pin to Channel 1 Track & Hold block. V CM = 1.2 V. V DIFF = 300 mV (r T = 100Ω). 36CKT&H Positive LVDS Clock Output pin to Channel 1 Track & Hold block. V CM = 1.2 V. V DIFF = 300 mV (r T = 100Ω). 37CKINT Negative LVDS Clock Output pin to Channel 0 Integrator block. V CM = 1.2 V. V DIFF = 300 mV (r T = 100Ω). 38CKINT Positive LVDS Clock Output pin to Channel 0 Integrator block. V CM = 1.2 V. V DIFF = 300 mV (r T = 100Ω). 39CKT&H Negative LVDS Clock Output pin to Channel 0 Track & Hold block. V CM = 1.2 V. V DIFF = 300 mV (r T = 100Ω). 40CKT&H Positive LVDS Clock Output pin to Channel 0 Track & Hold block. V CM = 1.2 V. V DIFF = 300 mV (r T = 100Ω). 41VCNT DLL Channel 0 Control Voltage monitor. 42V SS Ground. 43V DD Supply Voltage (3.3 V). 44V SS Ground. 45COARSEDLL Channel 0~3 external Voltage adjust. 46RSTSPI Slave Reset and Memory Preset. 47PWRSTIPower Reset Input. 48PWRSTOPower Reset (1.2 ms wide) Output.

16. USB  RS232: RS232  SPI (PIC): 12/04/201316 Delay Chip Test Board Schematics Coarse (DAC):