1. 26/11/02CROP meeting-Nicolas Dumont Dayot 1 CROP (Crate Read Out Processor)  Specifications.  Topology.  Error detection-correction.  Treatment (ECAL/HCAL & PRS/SPD).  Credit card PC.  Manpower-Schedule.

2. 26/11/02CROP meeting-Nicolas Dumont Dayot 2 Specifications - Design of a generic board for the ECAL/HCAL and PRS/SPD readout electronics. - Main tasks: - Validation and correction of the input data ( coming from the CROC). - Compression of the trigger information. - ADC 1D zero suppression. - Energy and neighbours computing (ECAL/HCAL). - DAQ formatting. - Run up to a 40 Khz event rate.

3. 26/11/02CROP meeting-Nicolas Dumont Dayot 3 Topology 14 CROP modules needed (with 3 input and 1 output optic fibbers for the CROC and DAQ interfaces). Calorimeter (half)ChannelsFront End CrateCROP External zone HCAL ECAL Medium zone Internal zone PRS SPD 750 1344 896 736 2x1344 2x896 2x736 2 3 2 2 2 1 11 1 1 1 1 1 1 Total = 7 External zone Medium zone Internal zone ECAL Left One CROP module will be associated with one calorimeter zone to facilitate the neighbours processing.

4. 26/11/02CROP meeting-Nicolas Dumont Dayot 4 Input interface 111 000 1111 Data Block0 Header Block0 Block0 Block15 Block1-14 [23-21][19-16][15-0] Checksum Block0 011 110 000 1111 Data Block15 Header Block15 011 Checksum Block15 P P [20] Event = 16x34 words (24 bits). = 544 words (24 bits). BX-ID L0-ID P SPD PRS Trigger SPD PRS ADC P Header word PRS/SPD data word ECAL/HCAL data word

5. 26/11/02CROP meeting-Nicolas Dumont Dayot 5 Error detection-correction  Block verification: - Block format (34 words). - Horizontal and vertical parity => single error => correction. => double error => status. - Build the block status.  Event verification: - Event format (1 to 15 block). - L0-ID consistency. - BX-ID continuity. - Build the event status. <= horizontal parity vertical parity => 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 bit to invert

6. 26/11/02CROP meeting-Nicolas Dumont Dayot 6 Error detection-correction scheme GLINK decoding Block verification horizontal & vertical parity, format block status Status-Checksum FIFO Block FIFO 21 24 21 24 Block correction 23 Event format verification 1 2 24 FIFO (100 events) ALTERA ACEX1K50 4 mots Block0 data Block1 data 64 words 23 Status FIFOEvent FIFO 1 2 Block0 data Block1 data Block15 data 1024 words Bloc1 checksum Bloc0 status Bloc0 checksum Block1 status Event0 status Event1 status 2 mots 23 Output multiplexer 23 GLINK

7. 26/11/02CROP meeting-Nicolas Dumont Dayot 7 PRS / SPD treatment  ADC treatment : - The ADC value is stretched from 8 bits to 10 bits (integer format). - An 1D zero suppression is performed (threshold, PRS/SPD trigger on). - The data are formatted for the DAQ sending. - We want an option where all the channels are considered.  Trigger compression: - The ADC and trigger values are treated in parallel. - 8 consecutive triggers (line of a Front End Board) are grouped together and compare to 0. ID first channel 8 bits SPD 8 bits PRS

8. 26/11/02CROP meeting-Nicolas Dumont Dayot 8 PRS/SPD scheme

9. 26/11/02CROP meeting-Nicolas Dumont Dayot 9 ECAL / HCAL treatment  ADC treatment: - An 1D zero suppression is performed (threshold). - The energy is estimated : E = Gain x (ADC value - pedestal). - The eight neighbours are read. - The datas are formatted for the DAQ sending. - We want an option where all the channels are considered.  Triggers compression: - The ADC and trigger values are treated in parallel. - The 1D zero suppression is performed (threshold). - Two consecutive selected triggers are grouped together. ID first channel Trigger (first channel) Trigger (second channel) Channels Neighbours.

10. 26/11/02CROP meeting-Nicolas Dumont Dayot 10 ECAL/HCAL scheme

11. 26/11/02CROP meeting-Nicolas Dumont Dayot 11 Credit card PC  Goal: - To manage the CROP board through a PC (ethernet connection).  Interconnections: - JTAG bus (interconnections tests, FPGA programmation ). - Parallel bus (memory loading/reading). - I2C bus (configuration registers loading/reading).  To be thought: - To use CC-PC for the CROP self test or debugging. => emulate the inputs. => read out and analyse the results.

12. 26/11/02CROP meeting-Nicolas Dumont Dayot 12 Manpower-Schedule  Manpower : - 1 ½ persons for the design (+1 beginning 2003). - 1 person for the CAD.  Schedule : - Now : well advanced simulations. - First half 2003 : first prototype. - End 2003 : first prototype validated.