1. 1 Copyright © 2013 Elsevier Inc. All rights reserved. Chapter 8 Networks and Multiprocessors

2. 2 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 8.1 Scheduling overhead is paid for at a nonlinear rate.

3. 3 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 8.2 Power consumption trends for desktop processors [Aus04] © 2004 IEEE Computer Society.

4. 4 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 8.3 The two major multiprocessor architectures.

5. 5 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 8.4 The OSI model layers.

6. 6 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 8.5 Physical and electrical organization of a CAN bus.

7. 7 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 8.6 The CAN data frame format.

8. 8 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 8.7 Architecture of a CAN controller.

9. 9 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 8.8 Major elements of an automobile network.

10. 10 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 8.9 Structure of an I 2 C bus system.

11. 11 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 8.10 Electrical interface to the I 2 C bus.

12. 12 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 8.11 Format of an I 2 C address transmission.

13. 13 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 8.12 State transition graph for an I 2 C bus master.

14. 14 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 8.13 Typical bus transactions on the I 2 C bus.

15. 15 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 8.14 Transmitting a byte on the I 2 C bus.

16. 16 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 8.15 An I 2 C interface in a microcontroller.

17. 17 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 8.16 Ethernet physical organization.

18. 18 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 8.17 The Ethernet CSMA/CD algorithm.

19. 19 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 8.18 Exponential backoff times.

20. 20 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 8.19 Ethernet packet format.

21. 21 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 8.20 Protocol utilization in Internet communication.

22. 22 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 8.21 IP packet structure.

23. 23 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 8.22 The Internet service stack.

24. 24 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 8.23 CPU accelerators in a system.

25. 25 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 8.24 Single-threaded vs. multithreaded control of an accelerator.

26. 26 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 8.25 Components of execution time for an accelerator.

27. 27 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 8.26 Streaming data into and out of an accelerator.

28. 28 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 8.27 Evaluating system speedup in a single-threaded implementation.

29. 29 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 8.28 Evaluating system speedup in a multithreaded implementation.

30. 30 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 8.29 Block diagram of MPEG-2 compression algorithm.

31. 31 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 8.30 Block motion estimation.

32. 32 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 8.31 Block motion search parameters.

33. 33 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 8.32 Classes describing basic data types in the video accelerator.

34. 34 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 8.33 Basic classes for the video accelerator.

35. 35 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 8.34 Sequence diagram for the video accelerator.

36. 36 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 8.35 An architecture for the motion estimation accelerator [Dut96].

37. 37 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 8.36 A schedule of pixel fetches for a full search [Yan89].

38. 38 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 8.37 Object diagram for the video accelerator.

39. 39 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 8.38 Data stored on a compact disc.

40. 40 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 8.39 Spiral data organization of a compact disc.

41. 41 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 8.40 A compact disc mechanism.

42. 42 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 8.41 Laser focusing in a CD.

43. 43 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 8.42 CD laser pickup regions.

44. 44 Copyright © 2013 Elsevier Inc. All rights reserved. Figure 8.43 Computing platform for a CD player.

45. 45 Copyright © 2013 Elsevier Inc. All rights reserved. UN Figure 8.1

46. 46 Copyright © 2013 Elsevier Inc. All rights reserved. UN Figure 8.2

47. 47 Copyright © 2013 Elsevier Inc. All rights reserved. UN Figure 8.3

48. 48 Copyright © 2013 Elsevier Inc. All rights reserved. UN Figure 8.4

49. 49 Copyright © 2013 Elsevier Inc. All rights reserved. UN Figure 8.5

50. 50 Copyright © 2013 Elsevier Inc. All rights reserved. UN Figure 8.6

51. 51 Copyright © 2013 Elsevier Inc. All rights reserved. UN Figure 8.7

52. 52 Copyright © 2013 Elsevier Inc. All rights reserved. UN Figure 8.8

53. 53 Copyright © 2013 Elsevier Inc. All rights reserved. UN Figure 8.9