1. 16 Bit Logarithmic Converter Tinghao Liang and Sara Nadeau

2. 16 Bit Logarithmic Converter  Introduction  Motivation  Algorithm Explanation  High level description  Block diagram  Design strategy  Baseline performance  Performance goals  Improvement strategy  Improved performance  Layout  Conclusions and Future Work

3. Project Motivation  Logarithmic converters simplify computational needs  Multiplication/Division -> Addition/Subtraction  Power/Root -> Multiplication/Division  Real time DSP becoming more and more in demand, increased need for log converters to simplify computation demands  Explore interesting circuitry

4. Algorithm  Whole number portion of base two logarithm of binary input acquired by detecting leading 1  Decimal portion of base two logarithm of binary input approximated by mantissa  Ex: Input -> 29 10 or 11101 2 Binary answer -> 100.1101 Decimal answer -> 4.8579 Error -> 0.0454, or 0.9%

5. Implementation – Block Diagram

6. Baseline Design Strategy  Direct CMOS implementation of all circuit blocks  Use gates sized for matching rise and fall times from lab 2  Goal – functional circuitry

7. Implementation – Leading One Detector Functionality LOD4LOD16

8. Implementation – ROM Functionality

9. Implementation – Barrel Shifter Functionality

10. Baseline Design Results  50 MHz operation speed  5 mW power consumption

11. Improvement Strategy - Speed  Critical path  MSB’s pass through LOD and ROM prior to output  LSB’s need valid ROM output before barrel shifter output is valid  Critical block – 2:1 MUX  Appears in LOD as well as barrel shifter, often cascaded  Sized with logical effort  4-Input NOR also resized for minimum average delay

12. Improvement Strategy - Power  Power supply reduced to 2 V  Circuitry simplified  ROM circuit activated only when clock is low

13. Improvement Strategy - Functionality  Expanded from 8 bits to 16 bits  Added a flag to indicate zero input

14. Schematic Changes - MUX

15. Improved Design Results  77 MHz operation speed  1.7 mW power consumption

16. Layout – Register

17. Layout – Leading One Detector

18. Layout - ROM

19. Layout – Barrel Shifter

20. Improved Design Layout

22. Conclusions and Future Work  Conclusions  Functional base two log converter designed and simulated successfully  Speed and power consumption were both improved by design modifications  Improvements  Size ROM cell for better speed  Further optimize layout organization  Add error compensation circuitry  Build anti-logarithmic converter

23. Thank you!  Questions?