1. ESSCIRC 2003 tutorial, September 15, 2003 Interconnect-centric design for future SoC and NoC 1 A System Designer’s View on SoC Communication Architectures Prof. D. Stroobandt Dr. J. Dambre Ghent University, Belgium dstr@elis.UGent.be http://www.elis.UGent.be/~dstr/

2. ESSCIRC 2003 tutorial, September 15, 2003 Interconnect-centric design for future SoC and NoC 2 Outline Interconnect from a system designer’s perspectiveInterconnect from a system designer’s perspective Some optical interconnect solutionsSome optical interconnect solutions Research methodologies for evaluating interconnect alternativesResearch methodologies for evaluating interconnect alternatives

3. ESSCIRC 2003 tutorial, September 15, 2003 Interconnect-centric design for future SoC and NoC 3 The System-on-Chip (SoC) revolution Yesterday and Today Today and Tomorrow Design of IP blocks Virtual Components System-Chip Integration ASIC design Physical Components System-Board Integration IP-reuse Platform-based design Network-on- Chip (NoC) On-chip interconnect properties affect system design!

4. ESSCIRC 2003 tutorial, September 15, 2003 Interconnect-centric design for future SoC and NoC 4 Doubles Interconnects dominate Communication requirements increaseCommunication requirements increase

5. ESSCIRC 2003 tutorial, September 15, 2003 Interconnect-centric design for future SoC and NoC 5 old new Interconnects dominate Relative communication delay increasesRelative communication delay increases Interconnects do not scale as componentsInterconnects do not scale as components Relative delay gates wires Delay old new

6. ESSCIRC 2003 tutorial, September 15, 2003 Interconnect-centric design for future SoC and NoC 6 Source: IBM Interconnects dominate

7. ESSCIRC 2003 tutorial, September 15, 2003 Interconnect-centric design for future SoC and NoC 7 ? Interconnect from a system designer’s perspective: matching requirements with available and future technologies System-level specifications Technological interconnect/ component properties ? Required interconnect properties Impact on system performance

8. ESSCIRC 2003 tutorial, September 15, 2003 Interconnect-centric design for future SoC and NoC 8 Interconnect from a system designer’s perspective: system-level requirements system functionalitysystem functionality system performance: system tasks must be performed within given time spansystem performance: system tasks must be performed within given time span system cost: overall power budget, production cost, design cost,...system cost: overall power budget, production cost, design cost,... other system properties: reliability, working conditions, life span,...other system properties: reliability, working conditions, life span,...

9. ESSCIRC 2003 tutorial, September 15, 2003 Interconnect-centric design for future SoC and NoC 9 Interconnect from a technology designer’s perspective Technology development for individual components, e.g.: Standard cell library designStandard cell library design Low-k dielectrics researchLow-k dielectrics research Copper and other materialsCopper and other materials Physical properties of (combinations of) components, e.g.: efficiencyefficiency throughputthroughput crosstalkcrosstalk power budgetpower budget

10. ESSCIRC 2003 tutorial, September 15, 2003 Interconnect-centric design for future SoC and NoC 10 ? Interconnect from a system designer’s perspective: matching requirements with available and future technologies System-level specifications Technological interconnect/ component properties ? Required interconnect properties Impact on system performance Very wide gap to bridge

11. ESSCIRC 2003 tutorial, September 15, 2003 Interconnect-centric design for future SoC and NoC 11 Interconnect from a system designer’s perspective: matching requirements with available and future technologies Required properties of communication architecture Impact on system performance System-level communication specifications Technological link properties Communication architecture Impact on performance of communication architecture Required link properties System-level communication specifications

12. ESSCIRC 2003 tutorial, September 15, 2003 Interconnect-centric design for future SoC and NoC 12 System-level interconnect requirements raw demand: communicating parallel processing units (transistors up to networked computers)raw demand: communicating parallel processing units (transistors up to networked computers) performance: communication must be realized within certain timeperformance: communication must be realized within certain time cost of interconnect: overall power budget, production cost, design cost,...cost of interconnect: overall power budget, production cost, design cost,... other interconnect properties: reliability, working conditions, life span,...other interconnect properties: reliability, working conditions, life span,... Not all hard requirements: trade-offs can/must be made!!

13. ESSCIRC 2003 tutorial, September 15, 2003 Interconnect-centric design for future SoC and NoC 13 Interconnect demand network size (number of processing units)network size (number of processing units)

14. ESSCIRC 2003 tutorial, September 15, 2003 Interconnect-centric design for future SoC and NoC 14 Interconnect demand point-to-point vs. point-to-multipointpoint-to-point vs. point-to-multipoint network size (number of processing units)network size (number of processing units)

15. ESSCIRC 2003 tutorial, September 15, 2003 Interconnect-centric design for future SoC and NoC 15 8 8 8 8 32 8 64 8 8 8 8 8 Interconnect demand link multiplicitylink multiplicity point-to-point vs. point-to-multipointpoint-to-point vs. point-to-multipoint network size (number of processing units)network size (number of processing units)

16. ESSCIRC 2003 tutorial, September 15, 2003 Interconnect-centric design for future SoC and NoC 16 Interconnect demand static vs. dynamic demandstatic vs. dynamic demand link multiplicitylink multiplicity point-to-point vs. point-to-multipointpoint-to-point vs. point-to-multipoint network size (number of processing units)network size (number of processing units)

17. ESSCIRC 2003 tutorial, September 15, 2003 Interconnect-centric design for future SoC and NoC 17 Interconnect from a system designer’s perspective: matching requirements with available and future technologies Required properties of communication architecture Impact on system performance System-level communication specifications Technological link properties Communication architecture Impact on performance of communication architecture Required link properties

18. ESSCIRC 2003 tutorial, September 15, 2003 Interconnect-centric design for future SoC and NoC 18 The communication architecture (or interconnection network) communication architecture mapping

19. ESSCIRC 2003 tutorial, September 15, 2003 Interconnect-centric design for future SoC and NoC 19 The communication architecture (or interconnection network) communication architecture

20. ESSCIRC 2003 tutorial, September 15, 2003 Interconnect-centric design for future SoC and NoC 20 The communication architecture (or interconnection network) ring

21. ESSCIRC 2003 tutorial, September 15, 2003 Interconnect-centric design for future SoC and NoC 21 The communication architecture (or interconnection network) mesh

22. ESSCIRC 2003 tutorial, September 15, 2003 Interconnect-centric design for future SoC and NoC 22 The communication architecture (or interconnection network) bus

23. ESSCIRC 2003 tutorial, September 15, 2003 Interconnect-centric design for future SoC and NoC 23 The communication architecture (or interconnection network) dedicated

24. ESSCIRC 2003 tutorial, September 15, 2003 Interconnect-centric design for future SoC and NoC 24 The communication architecture (or interconnection network) architecture typearchitecture type static vs. reconfigurablestatic vs. reconfigurable reconfiguration timereconfiguration time latency / throughputlatency / throughput redundancyredundancy etc.etc. communication architecture

25. ESSCIRC 2003 tutorial, September 15, 2003 Interconnect-centric design for future SoC and NoC 25 Interconnect from a system designer’s perspective: matching requirements with available and future technologies Required properties of communication architecture Impact on system performance System-level communication specifications Technological link properties Communication architecture Impact on performance of communication architecture Required link properties

26. ESSCIRC 2003 tutorial, September 15, 2003 Interconnect-centric design for future SoC and NoC 26 The communication channel or link A link is defined from output of processing unit to input of processing unit Restrictions of electrical interconnect, e.g.: throughput and density limitations,throughput and density limitations, signal integrity problems (noise, coupling,...),signal integrity problems (noise, coupling,...), etc....etc.... have been driving force behind research into alternative interconnect technologies: optical interconnectoptical interconnect RF interconnectRF interconnect other, more exotic alternativesother, more exotic alternatives

27. ESSCIRC 2003 tutorial, September 15, 2003 Interconnect-centric design for future SoC and NoC 27 The optical link A link is defined from electrical out to electrical in driver source/ modulator pathway (free space, fiber, wave guide) detector receiver

28. ESSCIRC 2003 tutorial, September 15, 2003 Interconnect-centric design for future SoC and NoC 28 Outline Interconnect from a system designer’s perspectiveInterconnect from a system designer’s perspective Some optical interconnect solutionsSome optical interconnect solutions Research methodologies for evaluating interconnect alternativesResearch methodologies for evaluating interconnect alternatives

29. ESSCIRC 2003 tutorial, September 15, 2003 Interconnect-centric design for future SoC and NoC 29 Important optical link properties Behavioral: –clocking behavior: synchronous, asynchronous or something in between –timing parameters: latency, skew, … –power dissipation, speed-power product –aggregate bit rate, error rate Topological: point-to-point vs. broadcast or bus; parallelism (i.e., number of parallel channels) Metrical: distance covered; required density

30. ESSCIRC 2003 tutorial, September 15, 2003 Interconnect-centric design for future SoC and NoC 30 The interconnect space: examples Behavior Topology Metrics asynchronous locally synchronous globally synchronous single, P-P multiple, P-P single, SMP multiple, SMP intra-chip MCM board level cabinet backplane Link between L2-cache and main memory Parallel Datacom link Clock distribution tree

31. ESSCIRC 2003 tutorial, September 15, 2003 Interconnect-centric design for future SoC and NoC 31 Interconnect contexts: Telecom is not Datacom Link is not Short-haul Interconnect ParameterTelecom Datacom Link Short-haul Interconnect Use of wave length (nm) Multiple ’s, single- mode (1300, 1500) Single, multimode (850)Single, multimode (850, 980) Data rates Extremely high, single link, very high channel rate Aggregate rate high, moderate number of links, limited channel rate Aggregate rate very high, high number of links, limited channel rate Latency and skew UnimportantSkew should be limited, latency not very important Can both be very important for very short links Distance100s of m to km10 m to 300 m10 cm to 10 m TopologySingle, Point to pointParallel (4 – 36), point to point Highly parallel (64 – 256), point to point or multipoint Clocking behavior Asynchronous or plesiosynchronous Mesosynchronous or synchronous Embedding in electronic system No Yes

32. ESSCIRC 2003 tutorial, September 15, 2003 Interconnect-centric design for future SoC and NoC 32 Interconnect contexts: Telecom is not Datacom Link is not Short-haul Interconnect The “right” interconnect properties strongly depend on the system’s interconnect requirementsThe “right” interconnect properties strongly depend on the system’s interconnect requirements (Optical) interconnect solutions must be tailored to the system’s interconnect context(Optical) interconnect solutions must be tailored to the system’s interconnect context

33. ESSCIRC 2003 tutorial, September 15, 2003 Interconnect-centric design for future SoC and NoC 33 Where are the biggest questions? O ptical interconnect WAN LANcabineton-boardon-chip Telecom + data links Recent and ongoing research (OIIC, IO*) Future research *IST-Project “Interconnect by Optics” (http://www.intec.UGent.be/io/)

34. ESSCIRC 2003 tutorial, September 15, 2003 Interconnect-centric design for future SoC and NoC 34 What Could It Look Like ? 3-D extension of electrical on-chip interconnect fabric3-D extension of electrical on-chip interconnect fabric –highly compact and densely interconnected system –essentially 3-D routing environment, shorter average lengths, faster systems –increased routability of complex designs Other (hierarchical) interconnect schemes could be envisionedOther (hierarchical) interconnect schemes could be envisioned

35. ESSCIRC 2003 tutorial, September 15, 2003 Interconnect-centric design for future SoC and NoC 35 A demonstrator system OIIC Project (http://www.elis.UGent.be/~jvc/oiic/sysdemo.htm)

36. ESSCIRC 2003 tutorial, September 15, 2003 Interconnect-centric design for future SoC and NoC 36 In-package glass sheet solution An alternative pathway is based on waveguides in glass sheets This pathway is directly integrated in the PCB

37. ESSCIRC 2003 tutorial, September 15, 2003 Interconnect-centric design for future SoC and NoC 37 Outline Interconnect from a system designer’s perspectiveInterconnect from a system designer’s perspective Some optical interconnect solutionsSome optical interconnect solutions Research methodologies for evaluating interconnect alternativesResearch methodologies for evaluating interconnect alternatives

38. ESSCIRC 2003 tutorial, September 15, 2003 Interconnect-centric design for future SoC and NoC 38 ? ? ? ? Interconnect from a system designer’s perspective: matching requirements with available and future technologies Required properties of communication architecture Impact on system performance System-level communication specifications Technological link properties Communication architecture Impact on performance of communication architecture Required link properties

39. ESSCIRC 2003 tutorial, September 15, 2003 Interconnect-centric design for future SoC and NoC 39 Evaluating the impact of interconnect properties on system performance Within each type of system or application domain, individual designs and individual implementations differ  Want to evaluate interconnect alternatives across this variation, i.e., make a statistical statement about their benefits/drawbacks

40. ESSCIRC 2003 tutorial, September 15, 2003 Interconnect-centric design for future SoC and NoC 40 Evaluating interconnect alternatives: research methodologies Simulation: perform large number of experiments on significant number of relevant problem instances Statistical modeling: combine most important statistical properties from communication requirements and interconnect performance In the past: applied to evaluate (optical and electrical) interconnect

41. ESSCIRC 2003 tutorial, September 15, 2003 Interconnect-centric design for future SoC and NoC 41 Exploring interconnect alternatives in VLSI design Dedicated communication architecture: optimal assignment of processing units (placement) + optimal communication path (routing) Very large networks with fixed topology and single bit links that can be point-to-multipoint

42. ESSCIRC 2003 tutorial, September 15, 2003 Interconnect-centric design for future SoC and NoC 42 Exploring interconnect alternatives in VLSI design Links can be implemented in a single or in multiple technological variants Interconnect properties are strongly dependent on distance between connected blocks (wire length)

43. ESSCIRC 2003 tutorial, September 15, 2003 Interconnect-centric design for future SoC and NoC 43 Simulation: probing the effect of short-haul optical interconnects (OI) in FPGAs Perform a large number of implementation experiments* Onto a variety of multi-FPGA configurationsOnto a variety of multi-FPGA configurations Using public-domain benchmarks (ISPD98)Using public-domain benchmarks (ISPD98) Estimate maximum clock frequency of synchronous circuits * J.Dambre, H. Van Marck, and J. Van Campenhout, Proc. Photonic Interconnect ’99 OI

44. ESSCIRC 2003 tutorial, September 15, 2003 Interconnect-centric design for future SoC and NoC 44 Result: increase in operation speed possible with low-latency optical interconnect 3-D interconnect leads to performance gains if optical link latency is small enough3-D interconnect leads to performance gains if optical link latency is small enough Gains biggest for large and complex circuitsGains biggest for large and complex circuits Impact of circuit interconnect complexity for benchmarks ‘apex4’ (non-complex) and ‘i10’ (complex)

45. ESSCIRC 2003 tutorial, September 15, 2003 Interconnect-centric design for future SoC and NoC 45 Early performance evaluation needed

46. ESSCIRC 2003 tutorial, September 15, 2003 Interconnect-centric design for future SoC and NoC 46 Region where refinement is needed Pareto-optimal solution Pareto front/curve Infeasible region Inferior results Early performance evaluation needed Fast estimates as indication of whether or not a proposed solution is far from or near to the Pareto front. If it is far away: discard. If it is close: gradually improve estimation accuracy.

47. ESSCIRC 2003 tutorial, September 15, 2003 Interconnect-centric design for future SoC and NoC 47 Interconnect-centric HW design X=(ABCD+A+D+A(B+C)) Y=(A(B+C)+AC+D+A(BC+D)) Packaging and testing Fabrication Circuit design Physical design Logic design Functional design System specification Physical and technological a priori estimations

48. ESSCIRC 2003 tutorial, September 15, 2003 Interconnect-centric design for future SoC and NoC 48 Statistical modeling: Interconnect prediction for VLSI design Predict length distribution of interconnections in optimized placement Predict length distribution of interconnections in optimized placement Statistically characterize interconnect requirements Technology and design parameters

49. ESSCIRC 2003 tutorial, September 15, 2003 Interconnect-centric design for future SoC and NoC 49 Interconnect prediction for VLSI design Parameters from interconnect topology Technology and design parameters Wire length distribution Probabilistic: wire length variability across multiple layout runs Not : accurate lengths of individual wires for particular run!

50. ESSCIRC 2003 tutorial, September 15, 2003 Interconnect-centric design for future SoC and NoC 50 Components of the Physical Design Step Layout Layout generation CircuitArchitecture

51. ESSCIRC 2003 tutorial, September 15, 2003 Interconnect-centric design for future SoC and NoC 51 Net Terminal / pin The Three Basic Models Circuit model Placement and routing model Model for the architecture Pad Channel Manhattan grid using Manhattan metric Cell Logic block

52. ESSCIRC 2003 tutorial, September 15, 2003 Interconnect-centric design for future SoC and NoC 52 Interconnect prediction details SuggestedSuggestedreading: D. Stroobandt. A Priori Wire Length Estimates for Digital Design. Kluwer Academic Publishers, 2001, 324 pages

53. ESSCIRC 2003 tutorial, September 15, 2003 Interconnect-centric design for future SoC and NoC 53 Prediction of interconnect lengths in VLSI design

54. ESSCIRC 2003 tutorial, September 15, 2003 Interconnect-centric design for future SoC and NoC 54 Recent work on wire length distribution estimations Correlation: 0.800 -> 0.999 Correlation: 0.800 -> 0.999

55. ESSCIRC 2003 tutorial, September 15, 2003 Interconnect-centric design for future SoC and NoC 55 Correlation: 0.986 Average error: 6.57% Correlation: 0.986 Average error: 6.57% Recent work on wire length distribution estimations

56. ESSCIRC 2003 tutorial, September 15, 2003 Interconnect-centric design for future SoC and NoC 56 Interconnect prediction for VLSI design Parameters from interconnect topology Technology and design parameters Wire length distribution Interconnect lengths affect: costcost power dissipationpower dissipation yieldyield performance (clock cycle)performance (clock cycle) etc....etc....

57. ESSCIRC 2003 tutorial, September 15, 2003 Interconnect-centric design for future SoC and NoC 57 Prediction of minimal clock cycle in synchronous digital systems Distribution of gate and wire delays Distribution and expected value of minimal clock cycle Parameters from interconnect topology Technology and design parameters Wire length distribution

58. ESSCIRC 2003 tutorial, September 15, 2003 Interconnect-centric design for future SoC and NoC 58 Prediction of achievable clock cycle in VLSI design

59. ESSCIRC 2003 tutorial, September 15, 2003 Interconnect-centric design for future SoC and NoC 59 Extrapolation to future systems: –Roadmaps. –GTX* et al. Technology Extrapolation * A. Caldwell et al. “GTX: The MARCO GSRC Technology Extrapolation System.” IEEE/ACM DAC, pp. 693-698, 2000

60. ESSCIRC 2003 tutorial, September 15, 2003 Interconnect-centric design for future SoC and NoC 60 Interconnect prediction for three-dimensional systems Parameters from interconnect topology Technology and design parameters Additional parameter: Relative cost of 3D interconnectionRelative cost of 3D interconnection Wire length distribution Wire length distribution for 3D system

61. ESSCIRC 2003 tutorial, September 15, 2003 Interconnect-centric design for future SoC and NoC 61 Three-dimensional Chips Different asymptotic average wire length*Different asymptotic average wire length* * J. Van Campenhout, H. Van Marck, J. Depreitere, J. Dambre, “Optoelectronic FPGA’s” IEEE J. Sel. Topics in Quant. Electr. (5)2, 1999, pp. 306 -- 315 Two-dimensionalThree-dimensional Design size (logic blocks) not complex complex very complex

62. ESSCIRC 2003 tutorial, September 15, 2003 Interconnect-centric design for future SoC and NoC 62 Three-dimensional Chips Wire length distribution differs significantly*Wire length distribution differs significantly* * J. Van Campenhout, H. Van Marck, J. Depreitere, J. Dambre,``Optoelectronic FPGA’s” IEEE J. Sel. Topics in Quant. Electr. (5)2, 1999, pp. 306 -- 315Distribution Topological complexity Average wire length

63. ESSCIRC 2003 tutorial, September 15, 2003 Interconnect-centric design for future SoC and NoC 63 Effect of Anisotropy Benefits are lower if anisotropy is higher*Benefits are lower if anisotropy is higher* Number of layers (4096 gates) Average wire length 1428616101214 3 7.5 2.5 6 5 4 3.5 7 6.5 5.5 4.5 Cost = 1 Cost = 16 Cost = 8 Cost = 24 * J. Van Campenhout, H. Van Marck, J. Depreitere, J. Dambre,``Optoelectronic FPGA’s” IEEE J. Sel. Topics in Quant. Electr. (5)2, 1999, pp. 306 -- 315

64. ESSCIRC 2003 tutorial, September 15, 2003 Interconnect-centric design for future SoC and NoC 64 Prediction of routing resources (area) Layer assignment and effect of vias Layer assignment and effect of vias Estimation of required routing resources Estimation of required routing resources Parameters from interconnect topology Technology and design parameters Wire length distribution

65. ESSCIRC 2003 tutorial, September 15, 2003 Interconnect-centric design for future SoC and NoC 65 –Wire length estimation models (Donath, …) –Actual placement information Models of achievable routing Required versus available resourcesRequired versus available resources

66. ESSCIRC 2003 tutorial, September 15, 2003 Interconnect-centric design for future SoC and NoC 66 Required versus available resourcesRequired versus available resources Limited by routing efficiency, power/ground nets and via impact Models of achievable routing

67. ESSCIRC 2003 tutorial, September 15, 2003 Interconnect-centric design for future SoC and NoC 67 A Typical Layer Assignment Example Tier type 2 Tier type 1 Tier type 0 Wire length (mm) Delay (ps) Wire width (  m) 02400224Number of repeaters

68. ESSCIRC 2003 tutorial, September 15, 2003 Interconnect-centric design for future SoC and NoC 68 Optimal Layer Stack Monotonic? 5.4426 7.0002 19.3665 Tier 2 Tier 1 Tier 0 7.1285 20 18 16 14 12 10 8 6 4 2 0 Number of layers per tier type 20 18 16 14 12 10 8 6 4 2 0

69. ESSCIRC 2003 tutorial, September 15, 2003 Interconnect-centric design for future SoC and NoC 69 Possible Applications of Layer Assignment Models A priori yield estimates (design for manufacturability)*A priori yield estimates (design for manufacturability)* –Interconnect functional yield model for cuts and bridges –Relation to wire length distribution Total or average power estimatesTotal or average power estimates Total area estimatesTotal area estimates Prediction of wiring demands in FPGAs**Prediction of wiring demands in FPGAs** * P. Christie and J. Pineda de Gyvez. Pre-layout prediction of interconnect manufacturability. Proc. Intl. Workshop on System-Level interconnect Prediction, pages 125 – 131, March 2001. ** M. Hutton. Interconnect prediction for programmable logic devices. Proc. Intl. Workshop on System-Level interconnect Prediction, pages 125 – 131, March 2001.

70. ESSCIRC 2003 tutorial, September 15, 2003 Interconnect-centric design for future SoC and NoC 70 Interconnect prediction for Network-on-Chip systems Parameters from interconnect topology Technology and design parameters Additional parameters: Number and size of NoC islandsNumber and size of NoC islands Characteristics of the networkCharacteristics of the network Relative cost of network interconnectionRelative cost of network interconnection Wire length distribution Wire length distribution for NoC

71. ESSCIRC 2003 tutorial, September 15, 2003 Interconnect-centric design for future SoC and NoC 71 Technological properties that are most important for system performance Latency and throughput: average, dependence on network configuration and node assignment Reconfiguration time in relation to time-scale of communication requirement variations

72. ESSCIRC 2003 tutorial, September 15, 2003 Interconnect-centric design for future SoC and NoC 72 Summary From a system designer’s perspective, the evaluation of interconnect technologies is inevitably linked to an application domain and its interconnect requirementsFrom a system designer’s perspective, the evaluation of interconnect technologies is inevitably linked to an application domain and its interconnect requirements Technological properties that are most important for system performance are latency and throughputTechnological properties that are most important for system performance are latency and throughput For evaluating the benefits/drawbacks of interconnect solutions, simulation and statistical modeling can be and have been usedFor evaluating the benefits/drawbacks of interconnect solutions, simulation and statistical modeling can be and have been used System-level interconnect prediction techniques are particularly suited to technology and communication architecture explorationSystem-level interconnect prediction techniques are particularly suited to technology and communication architecture exploration