1. Interrupt Driven I/O on the Mano CPU Doing things decently and in order

2. Final Phase of Instruction Cycle Simulation FETCH DECODE EXECUTE CHECK FOR INTERRUPTS (CFI)

3. I/O Device Issues Devices operate asynchronously with respect to the CPU Devices operate slowly with respect to the CPU Devices must request service Devices must hold pending requests

4. Alternative I/O Approaches Polling – Cycle through I/O devices – Process as needed – Polling consumes CPU cycles Interrupts – Adds hardware complexity (IEN, FGI, FGO, TR, OUTR, INPR) – Complicates CU design (especially for pipelined CPUs)

5. Semantics for CFI Conditions for CFI: T 0 ’ T 1 ’ T 2 ’ IEN (FGI+FGO) – T 0 ’,T 1 ’, T 2 ’: Not during FETCH or DECODE (or EXECUTE!) – IEN: interrupts must be enabled – FGI or FGO: a device requests service – If T 0 ’ T 1 ’ T 2 ’ IEN (FGI+FGO), then R<-1 Actions required to switch to interrupt handler (What to do if R equals1.) – RT 0 : AR<-0, TR<-PC – RT 1 : M[AR]<-TR, PC<-0 – RT 2 : PC<-PC+1, IEN<-0, R<-0

6. Testing CFI Use an I/O script Script entries contain (see the assignment) – Request time – Input register values Tests will only assess input operations Conditions the device simulator implements – TimeCC ≥ Time[ nextRequest ] – FGI = 0

7. Processing Steps For Simulating Input Device Service Requests Conditions – There is a request for service – Time has advanced to the scripted request – Any previous input service request has acquired a value from the INPR and cleared FGI = 0. Actions – Copy the value into the INPR – Set FGI=1 – Advance the script cursor (to the next request)

8. A Problem What must happen before returning from the Interrupt Service Routine (ISR)? – IEN<-1 via the ION instruction How does control return from a subroutine? – BUN I ZRO Suppose a request for service is pending when ION is executed in the ISR – IEN and FGI are 1 => CFI transfers to ISR with a return to the BUN I !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!

9. Final Simulator Demonstration ADD an RTI instruction to the simulator – RTI has hexadecimal representation F020 – Uses 2 clock cycles to execute – Semantics: AR<-0, IEN<-1; PC<-M[AR] Use the script from the assignment Apply to CPUTest13.dat and CPUTest14.dat – CPUTest13.dat produces an infinite loop – CPUTest14.dat executes in exactly 457 clock cycles