1. EE 5340 Semiconductor Device Theory Lecture 24 – Spring 2011 Professor Ronald L. Carter ronc@uta.edu http://www.uta.edu/ronc

2. ©rlc L24-19Apr20112 Ideal 2-terminal MOS capacitor/diode x -x ox 0 SiO 2 silicon substrate V gate V sub conducting gate, area = LW t sub 0 y L

3. ©rlc L24-19Apr20113 Band models (approx. scale) EoEo EcEc EvEv q  ox ~ 0.95 eV metalsilicon dioxidep-type s/c q  m = 4.1 eV for Al EoEo E Fm E Fp EoEo EcEc EvEv E Fi q  s,p q  Si = 4.05eV E g,ox ~ 8 eV

4. ©rlc L24-19Apr20114 Flat band condition (approx. scale) E c,Ox EvEv AlSiO 2 p-Si q(  m -  ox )= 3.15 eV E Fm E Fp EcEc EvEv E Fi q(  ox -  Si )=3.1eV E g,ox ~8eV q  fp = 3.95eV

5. ©rlc L24-19Apr20115 Depletion for p-Si, V gate > V FB SiO 2 p-type Si V gate > V FB V sub = 0 E Ox,x > 0 x -x ox 0 t su b Acceptors Depl Reg

6. ©rlc L24-19Apr20116 Depletion for p-Si, V gate > V FB Fig 10.4b*

7. ©rlc L24-19Apr20117 Equivalent circuit for depletion Depl depth given by the usual formula = x depl = [2  Si (V bb )/(qN a )] 1/2 Depl cap, C’ depl =  Si /x depl Oxide cap, C’ Ox =  Ox /x Ox Net C is the series comb C’ Ox C’ depl

8. ©rlc L24-19Apr20118 Inversion for p-Si V gate >V Th >V FB V gate > V FB V sub = 0 E Ox,x > 0 Acceptors Depl Reg e - e - e - e - e -

9. ©rlc L24-19Apr20119 Inversion for p-Si V gate >V Th >V FB Fig 10.5*

10. ©rlc L24-19Apr201110 Approximation concept “Onset of Strong Inv” OSI = Onset of Strong Inversion occurs when n s = N a = p po and V G = V Th Assume n s = 0 for V G < V Th Assume x depl = x d,max for V G = V Th and it doesn’t increase for V G > V Th C d,min =  Si /x d,max for V G > V Th Assume n s > 0 for V G > V Th

11. ©rlc L24-19Apr201111 MOS Bands at OSI p-substr = n-channel Fig 10.9*

12. ©rlc L24-19Apr201112 Equivalent circuit above OSI Depl depth given by the maximum depl = x d,max = [2  Si |2  p |/(qN a )] 1/2 Depl cap, C’ d,min =  Si /x d,max Oxide cap, C’ Ox =  Ox /x Ox Net C is the series comb C’ Ox C’ d,min

13. ©rlc L24-19Apr201113 MOS surface states** p- substr = n-channel

14. ©rlc L24-19Apr201114 n-substr accumulation (p-channel) Fig 10.7a*

15. ©rlc L24-19Apr201115 n-substrate depletion (p-channel) Fig 10.7b*

16. ©rlc L24-19Apr201116 n-substrate inversion (p-channel) Fig 10.7*

17. ©rlc L24-19Apr201117 Values for gate work function,  m

18. ©rlc L24-19Apr201118 Values for  ms with metal gate

19. ©rlc L24-19Apr201119 Values for  ms with silicon gate

20. ©rlc L24-19Apr201120 Fig 10.15*  ms (V) N B (cm -3 ) Typical  ms values

21. ©rlc L24-19Apr201121 Flat band with oxide charge (approx. scale) EvEv AlSiO 2 p-Si E Fm E c,Ox E g,ox ~8eV E Fp EcEc EvEv E Fi q(  fp -  ox ) q(V ox ) q(  m -  ox ) q(V FB ) V FB = V G -V B, when Si bands are flat ExEx + -

22. ©rlc L24-19Apr201122 References * Semiconductor Physics & Devices, by Donald A. Neamen, Irwin, Chicago, 1997. **Device Electronics for Integrated Circuits, 2nd ed., by Richard S. Muller and Theodore I. Kamins, John Wiley and Sons, New York, 1986