1. Let’s Open Up New Fields for Next 10X! Koji Inoue Kyushu University, Japan ISLPED'08@Bangalore

2. We Need More Performance! But… High performance is exactly required more! – Supercomputing, Desktop, Laptop, Cellar Phone, Home Games, and so on But, power is a SERIOUS problem! – Device Reliability – Grobal Warming ISLPED'08@Bangalore http://www.meti.go.jp/press/20071207005/03_G_IT_ini.pdf 200620252050 12X 5X Total Power Consumption in Japan 250 200 150 100 50 Billions KW/h Need drastic improvement! –Not Incremental!

3. How? Fundamental concept for low-power has matured in “Our Current Field”! – DVS, DVFS, Selective Activation, Exploiting Prediction, and so on… Suggestion – Move to a new (or strange) field! – Orchestrate computing resources effectively! ISLPED'08@Bangalore

4. New Fields! Revisit the system stack from circuit/architecture level to algorithm level on new fields! ISLPED'08@Bangalore 3D-IC Implementation with Wireless Links Keio University Yokohama National University Nagoya University Superconducting rapid single-flux-quantum (SFQ) New Reconfigurable Devices Advanced Industrial Science and Technology

5. The Case for SFQ-RDP Project ISLPED'08@Bangalore RSFQ with new architecture 10 TFLOPS Desk-top Computer Kyushu University, Yokohama National University, Nagoya University, SRL/ISTEC

6. ISLPED'08@Bangalore Superconducting rapid single-flux- quantum (SFQ) : Device Level Gate delay [s] Bit energy [J] Energy-delay products Superconducting wire Ballistic propagation MCM developed by SRL

7. Large-Scale Reconfigurable Data-Path for SFQ : Architecture Level 1K FPUs operate at 80 GHz Re-configurable operand network Much simple organization for SFQ design (No feedback loops) Make a good balance between “Parallel Exe. Vs. Sequential Exe.” ISLPED'08@Bangalore

8. How To Exploit A Number of FPUs: Compiler Level Large DFGs are extracted from source codes They are executed in pipeline fashion SFQ-RDP is used as an “Efficient Accelerator” ISLPED'08@Bangalore Application Program DFG Extractor (w/ source level optimization) Mapping

9. How To Exploit A Number of FPUs: Algorithm Level ISLPED'08@Bangalore tei(4,4,4,4)= (((3+2*p*(4*PAx*PBx+PBx**2+PAx**2*(1+2*p*PBx**2)))*(3+2*q*(4*QCx*QDx+QDx**2+QCx**2*(1+2*q*QDx**2)))*f(0,t))/(p**2*q**2)+(4*(3+2*p*(4*PAx*PBx+PBx* *2+PAx**2*(1+2*p*PBx**2)))*PQx*(QCx+QDx)*(3+2*q*QCx*QDx)*f(1,t))/(p*q*(p+q))(4*(PAx+PBx)*(3+2*p*PAx*PBx)*PQx*(3+2*q*(4*QCx*QDx+QDx**2+QCx**2*(1+2*q*QDx**2 )))*f(1,t))/(p*q*(p+q))(8*(PAx+PBx)*(3+2*p*PAx*PBx)*(QCx+QDx)*(3+2*q*QCx*QDx)*(((p+q)*f(1,t))+2*p*PQx**2*q*f(2,t)))/(p*q*(p+q)**2)+(2*(3+2*p*(4*PAx*PBx+PBx**2+PAx**2 *(1+2*p*PBx**2)))*(3+q*(QCx**2+4*QCx*QDx+QDx**2))*(((p+q)*f(1,t))+2*p*PQx**2*q*f(2,t)))/(p*q**2*(p+q)**2)+(2*(3+p*(PAx**2+4*PAx*PBx+PBx**2))*(3+2*q*(4*QCx*QDx+Q Dx**2+QCx**2*(1+2*q*QDx**2)))*(((p+q)*f(1,t))+2*p*PQx**2*q*f(2,t)))/(p**2*q*(p+q)**2)+(4*(3+2*p*(4*PAx*PBx+PBx**2+PAx**2*(1+2*p*PBx**2)))*PQx*(QCx+QDx)*(3*(p+q)*f( 2,t)+2*p*PQx**2*q*f(3,t)))/(q*(p+q)**3)\+(8*(3+p*(PAx**2+4*PAx*PBx+PBx**2))*PQx*(QCx+QDx)*(3+2*q*QCx*QDx)*(3*(p+q)*f(2,t)+2*p*PQx**2*q*f(3,t)))/(p*(p+q)**3)(8*(PAx+ PBx)*(3+2*p*PAx*PBx)*PQx*(3+q*(QCx**2+4*QCx*QDx+QDx**2))*(3*(p+q)*f(2,t)+2*p*PQx**2*q*f(3,t)))/(q*(p+q)**3)(4*(PAx+PBx)*PQx*(3+2*q*(4*QCx*QDx+QDx**2+QCx**2*( 1+2*q*QDx**2)))*(3*(p+q)*f(2,t)+2*p*PQx**2*q*f(3,t)))/(p*(p+q)**3)+((3+2*p*(4*PAx*PBx+PBx**2+PAx**2*(1+2*p*PBx**2)))*(3*(p+q)**2*f(2,t)+4*p*PQx**2*q*(3*(p+q)*f(3,t)+p* PQx**2*q*f(4,t))))/(q**2*(p+q)**4)(8*(PAx+PBx)*(3+2*p*PAx*PBx)*(QCx+QDx)*(3*(p+q)**2*f(2,t)+4*p*PQx**2*q*(3*(p+q)*f(3,t)+p*PQx**2*q*f(4,t))))/(q*(p+q)**4)(8*(PAx+PBx)*( QCx+QDx)*(3+2*q*QCx*QDx)*(3*(p+q)**2*f(2,t)+4*p*PQx**2*q*(3*(p+q)*f(3,t)+p*PQx**2*q*f(4,t))))/(p*(p+q)**4)+(4*(3+p*(PAx**2+4*PAx*PBx+PBx**2))*(3+q*(QCx**2+4*QCx* QDx+QDx**2))*(3*(p+q)**2*f(2,t)+4*p*PQx**2*q*(3*(p+q)*f(3,t)+p*PQx**2*q*f(4,t))))/(p*q*(p+q)**4)+((3+2*q*(4*QCx*QDx+QDx**2+QCx**2*(1+2*q*QDx**2)))*(3*(p+q)**2*f(2,t) +4*p*PQx**2*q*(3*(p+q)*f(3,t)+p*PQx**2*q*f(4,t))))/(p**2*(p+q)**4)(4*p*(PAx+PBx)*(3+2*p*PAx*PBx)*PQx*(15*(p+q)**2*f(3,t)+4*p*PQx**2*q*(5*(p+q)*f(4,t)+p*PQx**2*q*f(5,t)) ))/(q*(p+q)**5)+(8*(3+p*(PAx**2+4*PAx*PBx+PBx**2))*PQx*(QCx+QDx)*(15*(p+q)**2*f(3,t)+4*p*PQx**2*q*(5*(p+q)*f(4,t)+p*PQx**2*q*f(5,t))))/(p+q)**5+(4*PQx*q*(QCx+QDx)*( 3+2*q*QCx*QDx)*(15*(p+q)**2*f(3,t)+4*p*PQx**2*q*(5*(p+q)*f(4,t)+p*PQx**2*q*f(5,t))))/(p*(p+q)**5)(8*(PAx+PBx)*PQx*(3+q*(QCx**2+4*QCx*QDx+QDx**2))*(15*(p+q)**2*f(3,t )+4*p*PQx**2*q*(5*(p+q)*f(4,t)+p*PQx**2*q*f(5,t))))/(p+q)**5+(8*(PAx+PBx)*(QCx+QDx)*(15*(p+q)**3*f(3,t)+30*p*PQx**2*q*(p+q)*(3*(p+q)*f(4,t)+2*p*PQx**2*q*f(5,t))8*p**3*P Qx**6*q**3*f(6,t)))/(p+q)**6+(2*(3+p*(PAx**2+4*PAx*PBx+PBx**2))*(15*(p+q)**3*f(3,t)30*p*PQx**2*q*(p+q)*(3*(p+q)*f(4,t)+2*p*PQx**2*q*f(5,t))+8*p**3*PQx**6*q**3*f(6,t)))/( q*(p+q)**6)+(2*(3+q*(QCx**2+4*QCx*QDx+QDx**2))*(15*(p+q)**3*f(3,t)30*p*PQx**2*q*(p+q)*(3*(p+q)*f(4,t)+2*p*PQx**2*q*f(5,t))+8*p**3*PQx**6*q**3*f(6,t)))/(p*(p+q)**6)  787 MUL, 261 ADD, 69 FUNC Computation of molecular orbital while (I < 1000): I ++:

11. Koji’s Message (from Core to Data-Center) Move to new fields! Orchestrate computing resources effectively! – Efficient acceleration (Parallelization, Specialization) – Make a good balance between many things (Concurrency Management) ISLPED'08@Bangalore

12. Thanks!! ISLPED'08@Bangalore

13. New Fields! Revisit the system stack from circuit/architecture level to algorithm level on emerging devices! ISLPED'08@Bangalore

14. SMAC :...::: SMAC SB ORN... ORN... : : : : ORN... ORN FPU SFQ RDP （ 32FPU×32chips ） （４ GFLOPS ／ FPU) 4.2 K CMOS CPU (1chip) Memory band width per MCM ： 256GB/ ｓ (=16GB/s ×16 channels) 1024FPU@MCM （３４ chips ） ×4MCM 2TB memory module （ FB-DIMM [DDR3@1333MHz, 128GB] ×16 modules ） SFQ 0.5um process