1. Modern VLSI Design 4e: Chapter 4 Copyright  2008 Wayne Wolf Topics n Combinational network delay. n Logic optimization.

2. Modern VLSI Design 4e: Chapter 4 Copyright  2008 Wayne Wolf Sources of delay n Gate delay: –drive; –load. n Wire: –lumped load; –transmission line.

3. Modern VLSI Design 4e: Chapter 4 Copyright  2008 Wayne Wolf Fanout n Fanout adds capacitance. source sink

4. Modern VLSI Design 4e: Chapter 4 Copyright  2008 Wayne Wolf Ways to drive large fanout n Increase sizes of driver transistors. Must take into account rules for driving large loads. n Add intermediate buffers. This may require/allow restructuring of the logic.

5. Modern VLSI Design 4e: Chapter 4 Copyright  2008 Wayne Wolf Buffers

6. Modern VLSI Design 4e: Chapter 4 Copyright  2008 Wayne Wolf Wire capacitance n Use layers with lower capacitance. n Redesign layout to reduce length of wires with excessive delay.

7. Modern VLSI Design 4e: Chapter 4 Copyright  2008 Wayne Wolf Placement and wire capacitance unbalanced load more balanced dvr g1 g2 g3 g4 dvr g1 g2 g3 g4

8. Modern VLSI Design 4e: Chapter 4 Copyright  2008 Wayne Wolf Path delay n Combinational network delay is measured over paths through network. n Can trace a causality chain from inputs to worst-case output.

9. Modern VLSI Design 4e: Chapter 4 Copyright  2008 Wayne Wolf Path delay example network graph model

10. Modern VLSI Design 4e: Chapter 4 Copyright  2008 Wayne Wolf Critical path n Critical path = path which creates longest delay. n Can trace transistions which cause delays that are elements of the critical delay path.

11. Modern VLSI Design 4e: Chapter 4 Copyright  2008 Wayne Wolf Delay model n Nodes represent gates. n Assign delays to edges—signal may have different delay to different sinks. n Lump gate and wire delay into a single value.

12. Modern VLSI Design 4e: Chapter 4 Copyright  2008 Wayne Wolf Critical path through delay graph

13. Modern VLSI Design 4e: Chapter 4 Copyright  2008 Wayne Wolf Reducing critical path length n To reduce circuit delay, must speed up the critical path—reducing delay off the path doesn’t help. n There may be more than one path of the same delay. Must speed up all equivalent paths to speed up circuit. n Must speed up cutset through critical path.

14. Modern VLSI Design 4e: Chapter 4 Copyright  2008 Wayne Wolf False paths n Logic gates are not simple nodes—some input changes don’t cause output changes. n A false path is a path which cannot be exercised due to Boolean gate conditions. n False paths cause pessimistic delay estimates.

15. Modern VLSI Design 4e: Chapter 4 Copyright  2008 Wayne Wolf Logic rewrites deep logic shallow logic

16. Modern VLSI Design 4e: Chapter 4 Copyright  2008 Wayne Wolf Logic transformations n Can rewrite by using subexpressions. n Flattening logic increases gate fanin. n Logic rewrites may affect gate placement.

17. Modern VLSI Design 4e: Chapter 4 Copyright  2008 Wayne Wolf False path example

18. Modern VLSI Design 4e: Chapter 4 Copyright  2008 Wayne Wolf Logic optimization n Logic synthesis programs transform Boolean expressions into logic gate networks in a particular library. n Optimization goals: minimize area, meet delay constraint.

19. Modern VLSI Design 4e: Chapter 4 Copyright  2008 Wayne Wolf Technology-independent optimizations n Works on Boolean expression equivalent. n Estimates size based on number of literals. n Uses factorization, resubstitution, minimization, etc. to optimize logic. n Technology-independent phase uses simple delay models.

20. Modern VLSI Design 4e: Chapter 4 Copyright  2008 Wayne Wolf Technology-dependent optimizations n Maps Boolean expressions into a particular cell library. n Mapping may take into account area, delay. n May perform some optimizations on addition to simple mapping. n Allows more accurate delay models.