1. Orsay’s proposition for the L2  trigger system detailed description of the architecture distribution of the work costs schedule firmware Bernard Lavigne, Philippe Cros, Pierre Petroff, Laurent Duflot March the 13 th, 2001

2. CPU board Processor : Pentium III 850 MHz Dimensions : 6U Make : VMIC Type : VMIVME-7740 CPU board Processor : Pentium III 850 MHz Dimensions : 6U Make : VMIC Type : VMIVME-7740 Trigger Crate Trigger adaptation board Function : interface between the trigger crate and the processor board Trigger adaptation board Function : interface between the trigger crate and the processor board PCI bus 33 MHz, 32 bits VME bus Magic bus 128 data bits 32 add bits 20 MHz ECL signals L2 trigger mosaic of boards

3. 6U board 366 mm 160 mm 400 mm 233 mm 9U board Dimensions

4. Hard drive The proportions of the boards are respected 6U board 9U board mezzanine board Geometry of the boards

5. The proportions of the boards are respected 6U board9U board Geometry of the boards (profile view) Hard drive 9U board PCI interface 6U components sidemezzanine components side 9U components side (a few thin (height : 1.20 mm) TTL drivers will be on the other side) TTL drivers ~12mm

6. Hard drive 6U board 9U board Add-on Magic bus PCI VME EIDE mezzanine board drivers : electrical isolation VME electrical conversion to ECL Display The proportions of the boards are respected Electronics functions FIFOs : DMA storing PCI / Add-on interface Add-on / Magic bus interface & PCI / Magic bus arbitration FPGA 20 MHz 33 MHz

7. Hard drive 6U board 9U board Add-on Magic bus PCI Control signals VME EIDE mezzanine board Altera APEX 20K200 Fineline BGA 484 AMCC S5935 PQFP 160 TTL driver TTL driver TTL drivers FIFOs VME clk40MHz EPROM ECL drivers Display The proportions of the boards are respected Electronics placement

8. FPGA pin limited wide logics capacity (8320 cells, 13 kB mem) high rate low voltage BGA package unique FPGA flexibility inputs-outputs known beforehand

9. Magic bus Control signals from J1 and J2 connectors FIFOs output data and control signals ECL drivers data and control signals Display FPGA details 195 32 +5 TTL drivers control signals 5 Altera APEX 20K200 Fineline BGA 484 20 Add-on bus 60 32+ 2 EPROM 5 5 Clock 1 Switches 4 Total : 366 signals out of 376 available when unclear, the given count is approximative by excess 23.2 mm height : 1.86 mm the geomtry of the input/output pins is not respected

11. The proportions of the boards are respected 9U board from the factory

12. Add-on Magic bus EIDE Altera APEX 20K200 Fineline BGA 484 TTL driver TTL driver TTL drivers FIFOs clk40MHz EPROM ECL drivers The proportions of the boards are respected most components are assembled

13. Add-on Magic bus EIDE Altera APEX 20K200 Fineline BGA 484 TTL driver TTL driver TTL drivers FIFOs clk40MHz EPROM ECL drivers The proportions of the boards are respected the inside cut is sawed, the VME connectors are soldered

14. Add-on Magic bus EIDE Altera APEX 20K200 Fineline BGA 484 TTL driver TTL driver TTL drivers FIFOs clk40MHz EPROM ECL drivers The proportions of the boards are respected the front pannel and support bars are screwed

15. PCI the mezzanine board is relatively simple AMCC S5935 PQFP 160 add-on EPROM If all signals don’t pass through 2 PMC connectors, the board is enlarged to receive a 3rd one

16. The proportions of the boards are respected 6U board 9U board mezzanine board Grounding of the boards backplane

17. PCBs and hardware to design a 9U board a mezzanine board the 9U front panel the aluminium support bars no modification on the 6U board

18. Manpower at Orsay schematics, firmware : Bernard Lavigne, Philippe Cros (+ a technician if necessary) tests : Bernard Lavigne, Philippe Cros, Pierre Petroff, Laurent Duflot PCB design : board design group front panel, support bars, mechanics questions : mechanics group production, assembly : private companies

19. Costs (US $) prototype (3)production (30) PCB1700 1100 Components900 500 Assembly 200 400 Total2000 3350 Whole budget : $ 70000 The front panel and mechanics components are taken in account in the components budget The costs don’t count the CPU board, neither the engineering cost which is around $20000 PCB250150 Components10050 Assembly00 assembled at Orsay nota : 9U mezzanine

20. Schedule for the prototype marchaprilmayjunejulyaugustseptember schematics PCB designproduction tests software assembly schematics PCB designproduction firmware assembly 9U l2  system mezzanine front panel / bars

21. Firmware composed of blocks : necessity of a documentation with input-outputs-functionality of each block distribution of the blocks : Maryland : Magic bus, PIO, TSI, DMA Orsay : Add-on, DMA ? common language : Verilog, AHDL, VHDL ? most complex part of the project, the development should start soon

22. FIFOs output data and control signals ECL drivers data and control signals Display FPGA blocks control signals from P1/P2 connectors Altera APEX 20K200 Fineline BGA 484 Add-on bus EPROM Clock Switches Add-on bus interfaceTSI PIO MB interface local bus DMA ECL signals Magic bus the geomtry of the input/output pins is not respected Other TTL drivers control signals

23. Conclusion : The solution we propose : cheap realistic schedule manpower and experience technically reliable flexible developments equally shared