1. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 1 ECE 406 – Design of Complex Digital Systems Lecture 4: Testing, Dataflow Modeling Spring 2009 W. Rhett Davis NC State University with significant material from Paul Franzon, Bill Allen, & Xun Liu

2. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 2 Announcements l HW#1 Due Today l HW#2 Due in 1 week » Make sure that hw2-2.v executes correctly with the command “ncverilog hw2-2.v” » Work through first to pages of Verilog Simulation Tutorial (on the Resources Page) to learn more l Labs Start This Week

3. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 3 Summary of Last Lecture l What is the format of a Verilog instantiation? l Are all parts of the instantiation required? l What is the order of the port-names in a gate instantiation? A module instantiation? l Can a reg variable be connected to the input port of an instance?

4. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 4 Today’s Lecture l Test-Benches l Behavioral (Data-Flow) Modeling

5. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 5 From Last Lecture module mux_2 (out, i0, i1, sel); input i0, i1, sel; output out; wire n_sel, x1, x2; or (out, x1, x2); and (x1, i0, n_sel); and (x2, i1, sel); not (n_sel, sel); endmodule out 2-to-1 Mux i0 i1 sel i0 sel i1 out x1 n_sel x2 2-to-1 Multiplexer How do we test this description?

6. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 6 Parts of a Verilog Module l Header: module ( ); l Parameter, Port, & Variable declarations l Functionality description » Structural –Instantiations of basic gates (T&M 6.2) –Instantiations of lower-level modules (T&M 1.4, 5) » Behavioral –Data-Flow (continuous assignments) (T&M 2.2, 6.3) –Procedural (initial & always blocks) (T&M 2.3,3) l Terminator: endmodule

7. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 7 A Typical Test-Bench l Header: module ; l Variable declarations l Functionality description » Instantiation of the Device Under Test (DUT) » initial block to describe the Stimulus and display the output l Terminator: endmodule

8. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 8 Choosing the Stimulus l Job of the Stimulus is to apply test vectors (input combinations) l If we want to be 100% certain that the module is working correctly, how many vectors must be applied by the stimulus? out 2-to-1 Mux i0 i1 sel

9. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 9 Choosing the Stimulus l Exhaustive testing quickly becomes impractical as the number of inputs grows. l Need to choose a reduced set of test vectors that exposes the most likely errors. » It’s up to you to figure out what kinds of errors you’re likely to make For this example, we’ll use the following vectors: i0i1sel 010 011 100 101

10. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 10 Variable Declarations l All variables in the test bench basically connect to the DUT l Variables connected to DUT outputs » Will these be declared as wire or reg? Why? l Stimulus variables (connected to DUT inputs) » Will these be declared as wire or reg? Why?

11. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 11 mux_2 Test Bench Write the module header, variable declarations, and instantiation for the mux_2 test-bench: out 2-to-1 Mux i0 i1 sel

12. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 12 mux_2 Test Bench Stimulus and terminator for the mux_2 test-bench: initial begin in0 = 0; in1 = 1; sel = 0;// vector #1 $display (“in0: %b in1: %b sel: %b out: %b”, in0, in1, sel, out); in0 = 0; in1 = 1; sel = 1;// vector #2 $display (“in0: %b in1: %b sel: %b out: %b”, in0, in1, sel, out); in0 = 1; in1 = 0; sel = 0;// vector #3 $display (“in0: %b in1: %b sel: %b out: %b”, in0, in1, sel, out); in0 = 1; in1 = 0; sel = 1;// vector #4 $display (“in0: %b in1: %b sel: %b out: %b”, in0, in1, sel, out); $finish; // not needed, but handy if you want to end earlier end endmodule

13. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 13 Running the Simulation You run the simulation, and the output looks like this: in0 = 0 in1 = 1 sel = 0 out = x in0 = 0 in1 = 1 sel = 1 out = x in0 = 1 in1 = 0 sel = 0 out = x in0 = 1 in1 = 0 sel = 1 out = x So what happened? Why was out an x?

14. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 14 Annotating Time Delays are introduced into the stimulus by inserting #nn at the beginning of a statement (where nn is the number of time units) Write the code to assign the hex values 1234 and 5678 into A and B simultaneously and then, 10 units of time later, assign the hex value 90AB is set into C:

15. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 15 mux_2 Test Bench w/ Time Stimulus for the mux_2 test-bench with 10 units of time between each vector: initial begin in0 = 0; in1 = 1; sel = 0;// vector #1 #10 $display (“in0: %b in1: %b sel: %b out: %b”, in0, in1, sel, out); in0 = 0; in1 = 1; sel = 1;// vector #2 #10 $display (“in0: %b in1: %b sel: %b out: %b”, in0, in1, sel, out); in0 = 1; in1 = 0; sel = 0;// vector #3 #10 $display (“in0: %b in1: %b sel: %b out: %b”, in0, in1, sel, out); in0 = 1; in1 = 0; sel = 1;// vector #4 #10 $display (“in0: %b in1: %b sel: %b out: %b”, in0, in1, sel, out); $finish; // not needed, but handy if you want to end earlier end

16. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 16 Re-running the Simulation Having made these revisions, the simulation is rerun and the simulation output is: in0 = 0 in1 = 1 sel = 0 out = 0 in0 = 0 in1 = 1 sel = 1 out = 1 in0 = 1 in1 = 0 sel = 0 out = 1 in0 = 1 in1 = 0 sel = 1 out = 0 Which is what we would expect from the 2-to-1 mux.

17. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 17 Using $display and $monitor l The $display task outputs the specified data whenever a $display statement is encountered in the sequential execution of the stimulus. l The $monitor task watches the variables listed in the $monitor command and produces an output whenever any one of them changes. l A single $monitor statement may suffice in a test fixture instead of a series of identical $display statements. l Only one $monitor statement can be in effect during a simulation (the last one always takes effect). l It’s common to use single $monitor statement and multiple $display statements.

18. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 18 Simplified mux_2 Stimulus initial begin $monitor($time, “in0: %b in1: %b sel: %b out: %b”, in0, in1, sel, out); in0 = 0; in1 = 1; sel = 0;// vector #1 #10 in0 = 0; in1 = 1; sel = 1;// vector #2 #10 in0 = 1; in1 = 0; sel = 0;// vector #3 #10 in0 = 1; in1 = 0; sel = 1;// vector #4 #10 $finish; end Use $time here to print out current simulation time

19. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 19 Waveform Files l Another way to display the output is to create waveform files ».vcd files ».trn files l Use waveform viewers like SimVision to display these files l Explained in the Verilog Simulation Tutorial

20. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 20 Exercise Write a complete 4-vector test-bench for mux_4bit:

21. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 21 Today’s Lecture l Test-Benches l Behavioral (Data-Flow) Modeling

22. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 22 Describing Logic with Operators l Recall that the following expression is legal in Verilog: sel ? B : A l “? :” is a ternary operator » (sel ? B : A) evaluates to B if sel is true and A if sel is false l If sel is one bit, and A,B are 4-bit vectors, then isn’t there an easier way to describe the 4-bit MUX?

23. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 23 Continuous Assignments l The next level of design abstraction above gate- level design is dataflow, which is a kind of behavioral description. l Dataflow descriptions are created with the use of continuous assignment statements. l The format of a continuous assignment statement is: assign = ; for example: assign Out = sel ? B : A;

24. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 24 How assign Works, Conceptually l What does continuous assignment mean for the purposes of port-connection rules, multiple assignments, etc.? The statement assign Out = f( a, b, c,...) ; is the same as instantiating a complex gate

25. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 25 Port Connection Rules l Is Out of type reg, wire or either? l Are sel, A, and B of type reg, wire or either? l What will happen if a continuous assignment is done twice to the same signal?

26. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 26 Four-Bit 2-to-1 MUX So the code for the 4-bit mux from the last lecture becomes: // Four-bit 2-to-1 multiplexer module mux_4bit (Out, A, B, sel); input [3:0] A, B; input sel; output [3:0] Out; assign Out = sel ? B : A; endmodule Note that we don’t need to incorporate the mux_2 module into this module.

27. Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 27 Summary l How many test vectors are in an exhaustive stimulus? l How do you annotate time in a stimulus? l What is the most convenient system task to print the output during a simulation? l What keyword do you use when creating a dataflow behavioral description?