1. Lab for Cell-Based IC Design
Tsung-Yi Wu

2. Design Flow Reference NC Verilog Scan Insertion RTL QA RTL Prime Time
Verification/
Analysis
Testing
RTL Work NC
Verilog
Scan
Insertion
RTL QA
RTL
Prime
Time
ATPG
FPGA
Migration DC
Verplex
LEC
Memory
BIST
Turbo
Fault
JTAG
GL Netlist
>0.18um
<=0.18um
Apollo
Blast
Fusion
Blast
Plan
Power/Timing Analysis
Nautilus DC
Start-RC
IR Drop SI
Layout
Layout

3. Example Verilog RTL Code (gcd.v) module gcd(clk,xi,yi,reset,gcd,done);
input clk,reset;
input [15:0] xi,yi;
output done;
output [15:0] gcd;
reg [15:0] gcd;
reg done;
clk)
begin: gcd_loop
reg [15:0] x,y;
if (reset) begin x <= xi; y <= yi; done <= 0; end
else if (!done) begin
if (x == y) begin gcd <= x; done <= 1; end
else if (x > y) x <= x - y;
else y <= y - x;
end
endmodule

4. Example Testbench (gcd_tb.v) module tb; reg clk,reset;
reg [15:0] xi,yi;
wire [15:0] gcd;
wire done;
gcd dut(clk,xi,yi,reset,gcd,done);
always #5 clk = ~clk;
clk) begin
$display("gcd=",gcd," done=",done, " x=",
dut.gcd_loop.x, " y=",dut.gcd_loop.y);
end
clk) if (done) $finish;
initial begin
clk = 0; reset = 1; xi = 27; yi = 15;
#10 reset = 0;
endmodule

5. RTL Simulation RTL Simulation Copy 2 Verilog files to your directory
source ~tywua/csh/ncsim.csh
verilog gcd_tb.v gcd.v

6. RTL Simulation
Simulation Result

7. Synthesis Synthesis Steps Run X-Win32 Copy syn.tcl to your directory
source ~/csh/synthesis.csh
design_vision &
In Design Vision command window, enter
source syn.tcl
Quit Design Vision

8. Synthesis
Synthesis Result

9. Synthesis Output Files timing.log: timing Report gcd.sdf: SDF file
gcd.gt.v: Gate Level Netlist

10. Debussy Trace Your Gate Level Netlist source ~tywua/csh/verdi64.cshrc
In Debussy
FileImport DesignFrom File
Click gcd.gt.v
Click Add
Click OK
Click AND Gate Icon

11. Gate Level Simulation Copy gt_ gcd_tb1.v to your directory
source gl_sim1.bat
source gl_sim2.bat

12. Gate Level Simulation
Simulation Results

13. Gate Level Simulation
Simulation Results