1. 1 CORPORATE INSTITUTE OF SCIENCE & TECHNOLOGY, BHOPAL DEPARTMENT OF ELECTRONICS & COMMUNICATIONS MICRO CODED CONTROLLER - PROF. RAKESH K. JHA

2. A LTERNATIVES FOR C ONTROL U NIT (CU) Hard-wired (hardware) Random logic, programmable logic array (PLA), or ROM Fast Inflexible Firmware Microprogrammed or microcoded CU Control implemented like a computer (microcomputer) Microinstructions Microprogramming Flexible Changes to instruction set possible Completely different instruction sets can be emulated Speed limited by microcomputer memory 2

3. H ARDWIRED CU: S INGLE -C YCLE Implemented by combinational logic. 3 Control logic opcode Datapath ALU control 3 2 To ALU ALUOp Control signals funct. code 6 6

4. 4 Instr. mem. PC Add Reg. File Data mem. 1 mux 0 0 mux 1 4 1 mux 0 Sign ext. Shift left 2 ALU Cont. CONTROL opcode MemWrite MemRead ALU Branch zero 0-15 0-5 11-15 16-20 21-25 26-31 ALU 0 mux 1 Shift left 2 0-25 Jump Single-cycle Datapath MemtoReg ALUOp ALUSrc RegDst RegWrite

5. S INGLE -C YCLE C ONTROL L OGIC InputsOutputs Instr.type R0000001001000100 lw lw1000110111100000 sw sw101011X1X0010000 beq000100X0X0001010 J000010XXX0X0XXX1 5 ALUOp0 ALUOp1 RegDst ALUSrc MemtoReg RegWrite MemRead MemWrite Branch Op5 Op4 Op3 Op2 Op1 Op0 Jump

6. S INGLE -C YCLE C ONTROL C IRCUIT 6 lw swbeqJR RegDst ALUSrc MemtoReg RegWrite MemRead MemWrite Branch ALUOp1 ALUOp0 Jump Op5 Op4 Op3 Op2 Op1 Op0

7. ALU C ONTROL L OGIC Inputs Outputs to ALU Instr.type From CU Funct. Code from IR (bits 0-5) 3-bit code Opera- tion ALUOp1ALUOp0F5F4F3F2F1F0 lw, sw 00XXXXXX010Add B01XXXXXX110Subtract R 1XXX0000010Add 1XXX0010110Subtract 1XXX0100000AND 1XXX0101001OR 1XXX1010111 slt slt 7

8. ALU C ONTROL 8 ALU 3 zero result overflow Operation select from control Operation selectALU function 000AND 001OR 010Add 110Subtract 111Set on less than F3 F2 F1 F0 ALUOp1 ALUOp0 From Control Circuit Function code

9. M ULTICYCLE C ONTROL FSM 9 Instr. decode/reg. fetch/branch addr. ALU operation Write PC on branch condition Write memory data Write jump addr. to PC Write register Read memory data Instr. fetch/ adv. PC Compute memory addr. Write register lw or sw lw sw R B J Start State 0 1 23 45 6 7 8 9 Inputs: 6 opcode bits Outputs: 16 control signals

10. S TATES AND O UTPUTS Suppose 10 states are encoded 0000 through 1001. State code completely determines 16 control signals (Moore machine). States 0 (0000), 3 (0011) and 6 (0110) Next state ← present state + 1 State 1 (0001) – opcode must decide next state State 2 (0010) for lw or sw State 6 (0110) for R-type of instruction State 8 (1000) for branch instruction State 9 (1001) for jump instruction State 2 (0010) – opcode must decide next state State 3 (0011) for lw State 5 (0101) for sw States 4 (0100), 5 (0101), 7 (0111), 8 (1000) and 9 (1001) – next state is unconditionally 0 (0000) 10

11. A P ROGRAM -L IKE I MPLEMENTATION 11 Instr. decode/reg. fetch/branch addr. ALU operation Read memory data Instr. fetch/ adv. PC lw or sw lw sw R B J Start State 0000 0001 0010 0011 0100 0101 0110 0111 10001001 Inputs: 6 opcode bits Outputs: 16 control signals Compute memory addr. Write jump addr. to PC Write register Write memory data Write register Write PC on branch condition

12. I MPLEMENTING WITH ROM 12 Control PLA or ROM 16 words Four flip-flops 16 control signals PLA input or ROM address 6-bit opcode State sequencer Select one of 4 ways 16 2 4 6

13. ROM AND S TATE S EQUENCER 13 Control ROM Sixteen 18-bit words 4-bit address 4-bit state flip-flops 16 2 Control signals to datapath 4 4 0001 MUX 11 10 01 00 0000 AddrCtl go to 00 st. 0 11 st. + 1 01 st. 2,6,8,9 10 st. 3,5 Dispatch ROM 2Dispatch ROM 1 Adder 6 6-bit Opcode from IR Address Advance state 4 ROM Address sw, lw, R, B or J sw or lw

14. D ISPATCH ROM C ONTENTS 14 Dispatch ROM 1 InstructionAddress(Opcode)Content lw1000110010 sw1010110010 R0000000110 B0001001000 J0000101001 Dispatch ROM 2 InstructionAddress(Opcode)Content lw1000110011 sw1010110101 Each dispatch ROM has sixty-four 4-bit words Address is 6-bit opcode Content is next state (4-bits)

15. C ONTROL ROM C ONTENTS Control ROM has sixteen 18-bit words: bits 0-1, AddrCtl to control mux bits 2-17, sixteen control signals for datapath Address is 4-bit state of control machine Addr. bits 17-2 bits 17-2 bits 1-0 bits 1-0 0000100101000000100011 0001000000000001100001 0010000000000001010010 0011001100000000000011 0100000000100000001000 0101001010000000000000 0110000000000100010011 0111000000000000001100 1000010000001010010000 1001100000010000000000 15

16. M ICROPROGRAM : B ASIC I DEA The control unit in a computer generates an output (sequence of control signals) for each instruction. Suppose we break down each instruction into a series of smaller operations (microinstructions), such as, fetch, decode, etc. Then, implement the control unit as a small computer (within the computer) that executes a sequence of microinstructions (microprogram) for each instruction. M. V. Wilkes, “The Best Way to Design an Automatic Calculating Machine,” Report of Manchester University Computer Inaugural Conference, pp. 16-18, 1951. Reprinted in E. E. Swartzlander (editor), Computer Design Development: Principal Papers, pp. 266-270, Rochelle Park, NJ: Hayden, 1976. 16

17. M ICROCODED C ONTROL U NIT 17 Sixteen 18-bit words 4-bit address 4-bit state flip-flops 16 2 Control signals to datapath 4 4 0001 MUX 11 10 01 00 0000 AddrCtl Dispatch ROM 2Dispatch ROM 1 Adder 6 Opcode from IR Address Microcode memory μPC Address select logic Microcode word Sequencing field lw or sw sw, lw, R, B or J ROM address

18. I MPLEMENTING THE I DEA Use a memory type implementation for control unit. Create a software infrastructure to automatically translate instructions into memory data (microcode): Microinstructions – define a machine language in which instructions can be described Microprogram – an instruction described as a sequence of microinstructions Microassembler – converts microprogram to (binary) microcode Is there a micro-compiler? 18

19. M ICROPROGRAMMING A microinstruction set is defined. To program the control of a computer for an instruction set, a programmer writes a microprogram for each machine instruction. Each micrprogram is converted into microcode, specific to the datapath hardware, by a microassembler and the entire microcode is loaded in the microcode memory of the control unit (CU). 19

20. 20 THE END