Presentation is loading. Please wait.

Presentation is loading. Please wait.

Treasure Chess ECE 477 Team 2 - Spring 2013 Parul Schroff, Brock Caley, Sidharth Malik, Jeremy Stork Design Review.

Similar presentations


Presentation on theme: "Treasure Chess ECE 477 Team 2 - Spring 2013 Parul Schroff, Brock Caley, Sidharth Malik, Jeremy Stork Design Review."— Presentation transcript:

1 Treasure Chess ECE 477 Team 2 - Spring 2013 Parul Schroff, Brock Caley, Sidharth Malik, Jeremy Stork Design Review

2 Outline Project overview Project-specific success criteria Block diagram Component selection rationale Packaging design Schematic and theory of operation PCB layout Software design/development status Project completion timeline Questions / discussion

3 Project Overview A voice controlled chess game that can display possible moves for the chess piece selected by the player RGB LED matrix panel to display the chess board and the current state of the game OLED to display other game statistics Separate microcontrollers and a processor dedicated to the each of the game logic, display, and voice recognition

4 Project Specific Success Criteria 1.An ability to correctly output the current state of the game. 2.An ability to select and move a piece on the chess board with voice commands. 3.An ability to show players' possible moves for a piece they have selected. 4.An ability to keep track of in-game statistics such as time and pieces lost during the play. 5.An ability to tell the player when a move is illegal, or when they are in check/checkmate state.

5 Block Diagram

6 Component Selection Rationale Game Logic Micro - PIC24FJ128GA006 128 kB of flash memory for chess logic 2 SPI channels for LCD Display 1 I 2 C for transmitting data to display control micro 1 UART channels for input from the voice recognition micro 53 Max I/O pins 8 MHz of operating frequency

7 Voice Recognition Micro – dsPIC33FJ128GP202 Speech Recognition Capability 128 kB of flash memory 1 UART channels to talk to the game logic micro High-Speed ADC Module 21 Max I/O pins 7.37 MHz of operating frequency

8 Display Logic Micro – PIC24EP512GU810 512 kB of flash memory 12 PWM channels with resolution of 50 MHz for fast display refreshing 83 Max I/O pins 7.37 MHz of operating frequency

9 Voice Band CODEC with Mic – Si3000 ATD conversion Amplifying capability Good documentation

10 16x32 RGB LED Matrix Panel Display Limited options More convenient than having each square of the chess board as an individual matrix Reasonable cost as compared to others Good documentation

11 OLED Display – NDH-0216KZW-AB5 Wide viewing angle and easy to read Since it was still within our budget, we moved forward with it

12 Packaging Design 210x412x30mm 8.25x16.25x1in 2 OLED Panels 2 Keypads 2 Microphones 2 Push Buttons 1 Power Button 2 RGB LED Matrix (16x32)

13 Packaging Design

14

15 Overall Schematic

16 Mic/Codec

17

18 Voice Recognition Micro

19

20 Game Logic Micro

21

22 Display Micro

23

24 Power Supply

25

26 Keypad Encoders

27 LCD Shift Regs

28 4 and 8 Channel Regulators

29 PCB Layout 5V Power Supply Unit 3.3V Power Supply Unit Disp uC GL uC VR uC Headers Encoder Shift Reg Level Translators

30 PCB Components Power Supply (2) Keypad Encoders (2) Microcontrollers (3) Audio Codec (1) Analog Mux (1) Shift Registers (2) 8-bit Level Translators (2) 4-bit Level Translators (2) RJ-11 Connectors (3) Push Buttons for Reset (3)

31 PCB Constraints Trace Size Power Rail: 5V Rail – Will be at least 40 mils wide. 3.3 V Rail – Will be 15 mils wide. All other traces will be 10 mils wide. Keypad Encoder is a DIP Package.

32 PCB Layout PCB – 10mm x 30mm

33 PCB w/GND Plane

34 PCB w/o GND Plane Power Supply 5V Power Supply 3.3V Display Logic uC Game Logic uC VR uC w/ Codec

35 5V Power Supply

36 3.3V Power Supply

37 Display Logic Microcontroller

38 Game Logic Microcontroller

39 GL uC w/ Inputs

40 Voice Recognition uC w/ Codec

41 Software Development Status Basic “Heart-Beat” check programs Interfaced PIC24FJ128GA010 with the LCD display using a simple program Game Logic implementation in C in progress: basic input output, check if the move played is legal, display possible moves for the piece selected by the player, etc.

42 Project Completion Timeline Mar 3 - Mar 8 Finish and submit the PCB Layout Mar 18 - Mar 24 Complete Game logic and start interfacing it with the micro. Continue working on Voice Recognition and display logic. Start testing the PCB. Mar 25 - Mar 31 Continue interfacing game logic with the micro. Begin interfacing voice recognition and display logic with the micro. Start populating the PCB with the micros and other components. Apr 1- Apr 7 Finish individual components Apr 8 - Apr 13 Connect individual components

43 Project Completion Timeline Apr 14 – Apr 20 Troubleshoot. Start Packaging. Start documentation: poster, final report, lab notebook, peer review Apr 21- Apr 28 Test and Debug. Finish Packaging. Finish documentation: poster, final report, lab notebook, peer review May 11 Graduate? Maybe???? Apr 29 – May 1 Test. Debug. Test. Complete.

44 Questions

45 Block Diagram

46 Schematic

47 PCB Layout 5V Power Supply Unit 3.3V Power Supply Unit Disp uC GL uC VR uC Headers Encoder Shift Reg Level Translators

48 PCB w/o GND Plane


Download ppt "Treasure Chess ECE 477 Team 2 - Spring 2013 Parul Schroff, Brock Caley, Sidharth Malik, Jeremy Stork Design Review."

Similar presentations


Ads by Google