1. International Symposium on Low Power Electronics and Design A Hybrid Display Frame Buffer Architecture for Energy-Efficient Display Subsystem Kyungtae Han, Alexander Min, Nithyananda Jeganathan, and Paul Diefenbaugh Intel

2. DRAM-Based display subsystem –DRAM is used as a display frame buffer to transport display contents to display panel. –Power consumption of DRAM frame buffering is significant as the resolution of screen is growing (4K, 8K display). 2 Status Quo

3. Lots of static area in typical display contents 3 Insights *fps: Frame per Second (max: 60), SL: Scan-line, MB: Macro-block, P: Pixel in changed frame “# of Read >> # of Write” Read Dominance (Intensive) - Data reading from the display frame is much more frequent than the writing of new data onto the frame buffer

4. Energy efficient memory for data read – Phase Change Memory (PCM) –Asymmetric power consumption in PCM –High power required for changing its structure for write 4 Insights - II PCM consumes less energy for data read than data write (E read << E write )

5. Combined two types of memory as one frame buffer. –DRAM for Dynamic Content –PCM for Static Content 5 Hybrid Display Frame Buffer Architecture Data flow in hybrid approach (PCM stores static contents and DRAM stores dynamic contents)

6. Separate and combine contents accordingly. Content hint from OS-guide (e.g., X Window Damage Extension*) or HW (e.g., Pixel-by-Pixel comparison). 6 Hybrid Display Frame Buffer Controller *Dynamic Image Detection Scheme (DIDS) shows only 1% overhead in CPU utilization

7. Number of changed frame (f) A frame is decomposed as high active (d) and low active area. 7 Display Content Model

8. Memory energy model Write (x) and read (y) amount in frame buffer 8 Frame Buffer Model

9. 9 Energy Comparison between DRAM and PCM Frame Buffer DRAM PCM

10. 10 Break-Even Between DRAM and PCM Frame Buffer DRAM is better PCM is better

11. 11 Energy Comparison Energy Comparison among DRAM-only, PCM-only and hybrid frame buffers Up-to 43% Energy Savings with Hybrid Frame Buffer

12. PCM has a short lifetime expectation with at most 10 7 write per bit cell before failure. Large memory size and wear leveling can mitigate the short lifetime of Hybrid frame buffer. 12 Lifetime Comparison Lifetime comparison map with wear leveling in 2GB memory (Pixel (P), Macroblock (MB), and Scaline (SL))

13. Mobile display contents exhibit a read-dominant property. The Hybrid Frame Buffer takes full advantage of the read-dominant access pattern of display contents. The Hybrid Frame Buffer architecture reduces frame buffer energy consumption by up to 43%, compared to the conventional DRAM-only frame buffer. 13 Conclusion