1. Sampling chip psTDC_02 Jean-Francois Genat – Herve Grabas Mary Heinz – Eric Oberla 1/27/2016 1 psTDC_02 presentation

2. Overall presentation : the principle 1/27/2016psTDC_02 presentation 2

3. Overall presentation : the chip architecture (dual readout) 1/27/2016psTDC_02 presentation 3

4. The timing generator: principle 1/27/2016psTDC_02 presentation 4 256 cells Fixed sampling window To the channels Variable sampling window To the channels 40MHz clock DLL out monitoring

5. The timing generator Same architecture conserved Ajustable delay with two voltages Fixed and variable window generation (improvement) 1/27/2016psTDC_02 presentation 5

6. The channels: principle 1/27/2016psTDC_02 presentation 6

7. The Channel Sampling window Buffer Comparator Counter - ADC 1/27/2016psTDC_02 presentation 7

8. The Sampling window More control logic Bigger input capacitance Same bandwidth 1/27/2016psTDC_02 presentation 8

9. The Buffer Better input dynamic A bit slower Use less current 1/27/2016psTDC_02 presentation 9 The Comparator Same spec Use less current

10. Control signal Ramp generator Ring oscillator Trigger (improvement) Selections unit for read out 1/27/2016psTDC_02 presentation 10

11. The ramp generator Improved range and linearity Hopefully fixed the in-chip coupling Buffer per channel 1/27/2016psTDC_02 presentation 11

12. The ring oscillator Added a fan-out: better clock distribution 1/27/2016psTDC_02 presentation 12

13. The Trigger Positive and negative pulse detection Delay before triggering Threshold level adjustable Bypass possibility 1/27/2016psTDC_02 presentation 13

14. The Readout Faster Better buffering Possible to select channels and block of 64 cells Debugging possible via analog input and output 1/27/2016psTDC_02 presentation 14

15. Debugging Fifth channel for sampling window observation Test structure: comparator and buffer Option for channel analog monitoring Resistance test structure More monitoring: ring oscillator, DLLout, ramp More bypassing 1/27/2016psTDC_02 presentation 15

16. Chip design Better layouting Better ESD protection Tools are well known Excpect the chip soon for tests 1/27/2016psTDC_02 presentation 16