1. Copyright (c) 2003 by Valery Sklyarov and Iouliia Skliarova: DETUA, IEETA, Aveiro University, Portugal

2. Permanent project block DIP buttons LEDs 1 0 0 1 S 1...S 8 L 1 L 2 L 3 L 4 B4B4 B1B1 Tested VHDL block Any project includes permanent component interacting with VHDL code. This enables us to get data from DIP switchers and buttons and to display results on LEDs and LCD VHDL block will be given for all considered constructions of VHDL. Tested VHDL block can be directly connected to the first block and it allows to verify any VHDL construction in the respective circuit Index: 1 Result: 8

3. divider can be used in order to examine all changes in VHDL code in visual mode

4. library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity VHDL_test is Port ( data_in : in std_logic_vector(7 downto 0); data_out : out std_logic_vector(3 downto 0); index_out: out std_logic_vector(3 downto 0); clk : in std_logic; reset : in std_logic); end VHDL_test; architecture Behavioral of VHDL_test is signal my_bus : std_logic_vector(3 downto 0); signal bit3, bit2, bit1, bit0 : std_logic; begin bit3 <= '0'; bit2 <= '1'; bit1 <= '1'; bit0 <= '1'; my_bus <= (bit3, bit2, bit1, bit0); data_out <= my_bus; end Behavioral; Result: 7 Aggregation is a grouping of values to form an array or record expression This is a positional association, where the values are associated with elements from left to right common libraries code of entity Example in VHDL_AF.zip

5. code of entity architecture Behavioral of VHDL_test is -- declaration of bit3,…,bit0 and my_bus begin bit3 <= '0'; bit2 <= '1'; bit1 <= '1'; bit0 <= '1'; my_bus bit3, 2=>bit2, 1=>bit1, 3=>bit0); data_out appears on LCD end Behavioral; Result: > This is named association The elements are explicitly referenced and the order is not taken into account Example in VHDL_AF.zip

6. code of entity architecture Behavioral of VHDL_test is -- declaration of bit3,…,bit0 and my_bus begin bit3 <= '0'; bit2 <= '1'; bit1 <= '1'; bit0 <= '1'; my_bus bit3, 2=>bit2, 1=>bit1, 3=>bit0); data_out appears on LCD end Behavioral; Result: > Example in VHDL_AF.zip

7. code of entity architecture Behavioral of VHDL_test is signal my_bus : std_logic_vector(3 downto 0); begin my_bus '1', others => '0'); data_out <= my_bus; -- value 3 appears on LCD end Behavioral; Result: 3 The elements can be grouped. The keyword others indicates the remaining elements Example in VHDL_AF.zip

8. code of entity architecture Behavioral of VHDL_test is type my_packet is record first_bit: std_logic; second_bit : std_logic; data: std_logic_vector (1 downto 0); end record; signal record_data: my_packet; begin record_data <= ('0', '1', "01"); data_out <= record_data.first_bit & record_data.second_bit & record_data.data;-- value 5 appears on LCD end Behavioral; Result: 5 Aggregates are used in order to assign a record Example in VHDL_AF.zip

9. code of entity architecture Behavioral of VHDL_test is type my_array is array(3 downto 0) of std_logic; type my_packet is array(0 to 5) of my_array; signal my_data: my_packet := (others => "0110"); begin data_out <= my_data(2)(3) & my_data(2)(2) & my_data(2)(1) & my_data(2)(0); -- value 6 appears on LCD end Behavioral; Result: 6 3210 std_logic my_array my_packet my_data aggregates and arrays Example in VHDL_AF.zip

10. code of entity architecture Behavioral of VHDL_test is type my_array is array(3 downto 0) of std_logic; type my_packet is array(0 to 5) of my_array; signal my_data: my_packet := (others => "0110"); begin data_out <= my_data(2)(3) & my_data(2)(2) & my_data(2)(1) & my_data(2)(0); -- value 6 appears on LCD end Behavioral; Result: 6 Example in VHDL_AF.zip

11. entity VHDL_test is Port ( data_in : in std_logic_vector(7 downto 0); data_out : out std_logic_vector(3 downto 0); index_out: out std_logic_vector(3 downto 0); clk : in std_logic; reset : in std_logic); end VHDL_test; Index: 0 Result: 4 Index: 1 Result: 4 Index: 2 Result: 4 Index: 3 Result: 9 Index: 4 Result: 4 Index: 5 Result: 8 Example in VHDL_AF.zip

12. architecture Behavioral of VHDL_test is type my_array is array(3 downto 0) of std_logic; type my_packet is array(0 to 5) of my_array; signal my_data: my_packet := (others => "0110"); process(reset,clk) variable my_ind : integer range 0 to 5; begin if reset = '1' then my_data "1000", 3=>"1001", others => "0100"); my_ind := 0; elsif rising_edge(clk) then data_out <= my_data(my_ind)(3) & my_data(my_ind)(2) & my_data(my_ind)(1) & my_data(my_ind)(0); index_out <= conv_std_logic_vector(my_ind,4); if my_ind = 5 then my_ind := 0; else my_ind := my_ind + 1; end if; end process; end Behavioral; The divider provides clock with ~ 1 Hz frequency initialization data output for given index my_ind output to display index on LCD forming a sequence 0,1,2,3,4,5 of indexes Example in VHDL_AF.zip

13. architecture ARCH_NAME of ENTITY_NAME is begin end ARCH_NAME; Items are visible in any process or block within the architecture entity VHDL_test is Port ( data_in : in std_logic_vector(7 downto 0); data_out : out std_logic_vector(3 downto 0)); end VHDL_test; architecture Behavioral of VHDL_test is signal operandA, operandB, result : std_logic_vector (3 downto 0); begin data_out <= data_in(7 downto 6) * data_in(5 downto 4); end Behavioral; Example in VHDL_AF.zip

14. entity VHDL_test is Port ( data_in : in std_logic_vector(7 downto 0); data_out : out std_logic_vector(3 downto 0)); end VHDL_test; architecture Behavioral of VHDL_test is signal operandA, operandB, result : std_logic_vector (3 downto 0); begin data_out <= data_in(7 downto 6) * data_in(5 downto 4); end Behavioral; 1 0 S 0...S 7 Result: 6 2 * 3 = 6 Example in VHDL_AF.zip

15. 1 2 3 4 Mode 1 (S 1 ): Mode 2 (S 2 ): Mode 3 (S 3 ): Example in VHDL_ASS.zip

16. StateCAD diagram for FSM Divider, which provides ≈ 1 Hz frequency for FSM (for visual mode) VHDL code of the FSM created by StateCAD Control of DIP switchers and LEDs FSM Example in VHDL_ASS.zip

17. LED1 LED2 LED3 LED4 SW1 SW2 SW3 Example in VHDL_ASS.zip

18. entity LCD_struc is Port ( switchers : in std_logic_vector(2 downto 0); LEDs : out std_logic_vector(3 downto 0); clk48 : in std_logic; rst : in std_logic); end LCD_struc; architecture Behavioral of LCD_struc is component LED_SW PORT (CLK,RESET,SW1,SW2,SW3: IN std_logic; LED1,LED2,LED3,LED4 : OUT std_logic); end component; component Divider Port ( clk48 : in std_logic; rst : in std_logic; loc_clk : out std_logic); end component; signal internal_clock : STD_LOGIC; begin FSM : Divider port map(clk48,rst,internal_clock); led_control : LED_SW port map(internal_clock,rst,switchers(2),switchers(1),switchers(0), LEDs(0),LEDs(1),LEDs(2),LEDs(3)); end Behavioral; switchers(2) switchers(1) switchers(0) Divider LED_SW clk48 rst loc_clk internal_clock CLK RESET SW1 SW2 SW3 LED1 LED2 LED3 LED4 LEDs(0) LEDs(1) LEDs(2) LEDs(3) LEDs : out std_logic_vector(3 downto 0); 48 MHz  1 Hz rst S3S3 S2S2 S1S1 L1L1 L2L2 L3L3 L4L4 LCD_struc switchers : in std_logic_vector (2 downto 0); Example in VHDL_ASS.zip

19. entity LCD_struc is Port ( switchers : in std_logic_vector(2 downto 0); LEDs : out std_logic_vector(3 downto 0); clk48 : in std_logic; rst : in std_logic); end LCD_struc; architecture Behavioral of LCD_struc is component LED_SW PORT (CLK,RESET,SW1,SW2,SW3: IN std_logic; LED1,LED2,LED3,LED4 : OUT std_logic); end component; component Divider Port ( clk48 : in std_logic; rst : in std_logic; loc_clk : out std_logic); end component; signal internal_clock : STD_LOGIC; begin FSM : Divider port map(clk48,rst,internal_clock); led_control : LED_SW port map(internal_clock,rst,switchers(2),switchers(1),switchers(0), LEDs(0),LEDs(1),LEDs(2),LEDs(3)); end Behavioral; connection switchers(2) switchers(1) switchers(0) Divider LED_SW clk48 rst loc_clk internal_clock CLK RESET SW1 SW2 SW3 LED1 LED2 LED3 LED4 LEDs(0) LEDs(1) LEDs(2) LEDs(3) LEDs : out std_logic_vector(3 downto 0); 48 MHz  1 Hz rst S3S3 S2S2 S1S1 L1L1 L2L2 L3L3 L4L4 LCD_struc switchers : in std_logic_vector (2 downto 0); Example in VHDL_ASS.zip

20. type type_name is array (range) of type_of_elements; type RAM is array (9 downto 0) of std_logic_vector(7 downto 0); signal my_RAM : RAM; architecture Behavioral of VHDL_test is type RAM is array (9 downto 0) of std_logic_vector(7 downto 0); signal my_RAM : RAM; begin process(clk,reset) variable tmp : integer range 0 to 9; begin if reset = '1' then tmp := 0; elsif rising_edge(clk) then my_RAM(tmp) <= data_in + conv_std_logic_vector(tmp,8); if (tmp < 9) then tmp := tmp + 1; else tmp := 0; end if; end if; end process; my_RAM(0) = “00110000” my_RAM(1) = “00110001” my_RAM(2) = “00110010” my_RAM(3) = “00110011” my_RAM(4) = “00110100” my_RAM(5) = “00110101” my_RAM(6) = “00110110” my_RAM(7) = “00110111” my_RAM(8) = “00111000” my_RAM(9) = “00111001” data_in = 00110000

21. object’attribute_name; process(clk,reset) begin if falling_edge(clk) then for i in my_RAM'reverse_range loop -- the result is “00111001” (ASCII – 9) data_out <= my_RAM(i); end loop; end if; end process; process(clk,reset) begin if falling_edge(clk) then for i in my_RAM'range loop -- the result is “00110000” (ASCII – 0) data_out <= my_RAM(i); end loop; end if; end process;

22. object’attribute_name; process(clk,reset) variable tmp : integer range 0 to 9; begin if reset = '1' then tmp := 0; elsif falling_edge(clk) then data_out <= my_RAM(tmp); index_out <= "000" & my_RAM(tmp)(my_RAM(tmp)'right); index_out <= "000" & my_RAM(tmp)(my_RAM(tmp)'left); index_out <= x"30" + conv_std_logic_vector((my_RAM'length)-1,8); --my_RAM'high - my_RAM'low + 1- the result is 9 index_out <= x"30" + conv_std_logic_vector(my_RAM(0)'length,8); if (tmp < 9) then tmp := tmp + 1; else tmp := 0; end if; end if; end process; index_out <= "000" & my_RAM(tmp)(my_RAM(tmp)'right); the most right bit the most left bit the result is “00111000” (ASCII – 8) length object’highthe upper bound of object object’lowthe lower bound of object object’eventTrue when signal object changes etc.

23. label: block (unsupported_in_ISE_optional_ guard_condition) declarations begin concurrent_statements end block label; Block permits to group concurrent statements within an architecture architecture -- …………………………….. -- …………… begin Programmable_MUX: block signal link : std_logic_vector(R-1 downto 0); begin MUX : Gen_Mux generic map(L=>8,R=>3) port map(link,X,MUX_OUT); MUX_RAM : RAM generic map(N=>3,deep=>8,R=>3) port map(clk,we,di,state,ar,link); end block Programmable_MUX; -- ……………. M RAM X link MUX_OUT state for reprogramming RAM

24. level: block signal m_out : std_logic; signal composed : std_logic_vector(R downto 0); begin composed <= ds & m_out; level_CC: Prog_Mux generic map(L=>8,R=>3) port map(clk,wem,di,ar,ds,X,m_out); level_RAM: RAM generic map(N=>3,deep=>16,R=>4) port map (clk,we,di,composed,ar,T); end block level; RAM M x0x0 x L-1 0 R-1 G blocks fdc 0 fdc R-1 y0y0 Output RAM y N-1 Y X RAM M x0x0 x L-1 0 R-1 X XY

25. case state is when "0000“ => a <= "00"; cpld_cs <= '1'; cpld_rw <= '1'; when "0001" => cpld_cs <= '0'; when "0010" => lpb <= d; when "0011" => cpld_cs <= '1'; when "0100" => a <= "10"; cpld_rw <= '0'; when "0101" => cpld_cs <= '0'; when "0110" => cpld_cs <= '1'; when "0111" => a <= "01"; cpld_cs <= '1'; cpld_rw <= '1'; when "1000" => cpld_cs <= '0'; when "1001" => dipswitch <= d; when "1010" => cpld_cs <= '1'; when others => cpld_cs <= '1'; end case; Interaction with DIP switches, push buttons and LEDs for trenz TE-XC2Se prototyping board see more details in Tutorial 2 CPLD XC9572XL DIP buttons LEDs a(2:1) cpld_rwcpld_cs 1 0 0 1 S 1...S 8 L 1 L 2 L 3 L 4 B4B4 B1B1

26. entity VHDL_test is Port ( data_in : in std_logic_vector(7 downto 0); --........................... process(clk,reset) variable tmp : integer; begin if falling_edge(clk) then tmp := conv_integer(data_in); case tmp is when 0 => index_out <= "0000"; when 1 to 5 => index_out <= "0001"; when 6|8|10 => index_out <= "0010"; when others => index_out <= "0011"; end case; end if; end process; converts std_logic_vector to integer data_in index_out “00000000” “0000” “00000001” “0001” “00000010” “0001” “00000011” “0001” “00000100” “0001” “00000101” “0001” “00000110” “0010” “00000111” “0011” “00001000” “0010” “00001001” “0011” “00001010” “0010” “00001011” “0011” “00001100” “0011” “00001101” “0011” “00001110” “0011” ………….. “0011”

27. entity VHDL_test is Port ( data_in : in std_logic_vector(7 downto 0); --........................... process(clk,reset) begin if falling_edge(clk) then case data_in is when "00000000" => index_out <= "0000"; when "00000001"| "00000010"| "00000011"| "00000100"| "00000101" => index_out <= "0001"; when "00000110"| "00001000"| "00001010" => index_out <= "0010"; when others => index_out <= "0011"; end case; end if; end process; data_in index_out “00000000” “0000” “00000001” “0001” “00000010” “0001” “00000011” “0001” “00000100” “0001” “00000101” “0001” “00000110” “0010” “00000111” “0011” “00001000” “0010” “00001001” “0011” “00001010” “0010” “00001011” “0011” “00001100” “0011” “00001101” “0011” “00001110” “0011” ………….. “0011”

28. process(clk,reset) begin if falling_edge(clk) then case data_in is when "00010110" => index_out <= "0000"; when "0001-0-0" => index_out <= "0001"; when "0000----" => index_out <= "0010 "; when others => index_out <= "0011"; end case; end if; end process; data_in index_out “00000000” “0010” “00000001” “0010” “………….” “0010” “00001111” “0010” “00010000” “0001” “00010001” “0011” “00010010” “0001” “00010011” “0011” “00010100” “0011” “00010101” “0011” “00010110” “0000” “00010111” “0011” “…………..” “0011” “00011000” “0001” “00011001” “0011” “00011010” “0001” “…………..” “0011” don’t care

29. component Divider Port ( clk48 : in std_logic; rst : in std_logic; loc_clk : out std_logic); end component; component Gen_Mux is generic (L : integer; R : integer); Port ( SEL : in STD_LOGIC_VECTOR(R-1 downto 0); X : in STD_LOGIC_VECTOR(L-1 downto 0); MUX_OUT : out STD_LOGIC); end component; Generic multiplexer component component_name generic (generic_list); port(port_list) end component

30. label: component_name generic map (generic_list) port map (port_list); architecture Behavioral of LCD_struc is component LED_SW Port (CLK,RESET,SW1,SW2,SW3: IN std_logic; LED1,LED2,LED3,LED4 : OUT std_logic); end component; component Divider Port ( clk48 : in std_logic; rst : in std_logic; loc_clk : out std_logic); end component; signal internal_clock : STD_LOGIC; begin FSM : Divider port map(clk48,rst,internal_clock); led_control : LED_SW port map(internal_clock,rst,switchers(2),switchers(1),switchers(0), LEDs(0),LEDs(1),LEDs(2),LEDs(3)); end Behavioral; Example in VHDL_ASS.zip

31. label: component_name generic map (generic_list) port map (port_list); architecture Behavioral of Prog_Mux is component Gen_Mux is generic (L : integer; R : integer); Port ( SEL : in STD_LOGIC_VECTOR(R-1 downto 0); X : in STD_LOGIC_VECTOR(L-1 downto 0); MUX_OUT : out STD_LOGIC); end component; --.................................................. signal link : std_logic_vector(R-1 downto 0); begin MUX : Gen_Mux generic map(L=>8,R=>3) port map(link,X,MUX_OUT); --.................................................. end Behavioral;

32. constant constant_name : type := value; architecture Behavioral of display is --....... constant line1: string(1 to 3) := " = ";-- see tutorial 3 --....... begin --....... architecture Behavioral of display is --....... constant ternary_vector : std_logic_vector(5 downto 0) := "01-1-0"; constant my_const : integer := 7; --....... begin --.......

33. entity Prog_Mux is generic (L : integer := 8; R : integer := 3); Port ( clk : in std_logic; we : in std_logic; di : in std_logic_vector(R-1 downto 0); ar : in std_logic_vector(R-1 downto 0); state : in STD_LOGIC_VECTOR(R-1 downto 0); X : in STD_LOGIC_VECTOR(L-1 downto 0); MUX_OUT : out STD_LOGIC); end Prog_Mux; entity entity_name is generic(generic_list); port(port_list) end entity_name;

34. on off For example: on off entity VHDL_test is Port ( index_out: out std_logic_vector(3 downto 0); --........................................ process(data_in) variable index : integer range 0 to 5; begin index := 0; index_out '0'); loop exit when index = 5; if data_in(index)= '1' then index_out <= conv_std_logic_vector(index,4); end if; index := index + 1; end loop; end process; exit; exit when condition; index_out keeps the number of the last DIP switch “on” from left to right the number of the last DIP switch, which is checked is 4 index_out = 2 0 1 2

35. exit; exit when condition; process(data_in) variable index : integer range; begin index := 0; index_out '0'); for index in data_in'reverse_range loop if index = 5 then exit; else if data_in(index)= '1' then index_out <= conv_std_logic_vector(index,4); end if; end loop; end process; The result is the same as in the previous example

36. exit; exit when condition; process(data_in) variable index : integer range; begin index := 0; index_out '0'); for index in data_in'range loop exit when index = 5; if data_in(index)= '1' then index_out <= conv_std_logic_vector(index,4); end if; end loop; end process; on off index_out keeps the number of the last DIP switch “on” from right to left index_out keeps the number of the last DIP switch “on” from left to right for index in data_in'reverse_range loop compare with the previous examples the number of the last DIP switch, which is checked is 6 i.e. only DIP switchers 6 and 7 are checked

37. exit ; process(data_in) variable index : integer; begin index := 0; index_out '0'); ext:for index in data_in'range loop int: for I in 0 to 7 loop exit ext when index = I; exit int when I = 4; end loop int; end loop ext; index_out <= conv_std_logic_vector(index,4); end process; The optional loop_label may be used to indicate which loop has to be exited label of external loop label of internal loop

38. on off index_out = “0001” for control_variable in range loop sequential statements end loop process (data_in) variable temp : std_logic; begin temp := '0'; for i in data_in'range loop temp := temp xor data_in(i); end loop; index_out <= "000" & temp; end process; on off index_out = “0000” tests parity process (data_in) variable temp : integer range 0 to 6; begin temp := 0; for i in 6 downto 0 loop if data_in(i) = '1' then temp := temp+1; end if; end loop; index_out <= conv_std_logic_vector(temp,4); end process; counts the number of “ones” in 7 first DIP switchers on off index_out = “0010” There are many other examples with for loop in this tutorial

39. function function_name (parameter_list) return type is begin end function_name architecture Behavioral of VHDL_test is function parity (input : std_logic_vector) return std_logic is variable temp : std_logic := '0'; begin for i in input'range loop temp := temp xor input(i); end loop; return temp; end parity; begin data_out <= "000" & parity(data_in); end Behavioral; function call for i in input'range loop temp := temp xor input(i); end loop; entity VHDL_test is Port ( data_in : in std_logic_vector(7 downto 0); data_out : out std_logic_vector(3 downto 0)); end VHDL_test; for our example i will be changed from 7 to 0 this function is valid for any size of input parameter - input Example in VHDL_AF.zip

40. function function_name (parameter_list) return type is begin end function_name architecture Behavioral of VHDL_test is function parity (input : std_logic_vector) return std_logic is variable temp : std_logic := '0'; begin for i in input'range loop temp := temp xor input(i); end loop; return temp; end parity; begin data_out <= "000" & parity(data_in); end Behavioral; Example in VHDL_AF.zip

41. function function_name (parameter_list) return type is begin end function_name architecture Behavioral of VHDL_test is function parity (input : std_logic_vector) return std_logic is variable temp : std_logic := '0'; begin for i in input'range loop temp := temp xor input(i); end loop; return temp; end parity; begin data_out <= "000" & parity(data_in); end Behavioral; Example in VHDL_AF.zip

42. Example in VHDL_AF.zip 1234

43. library IEEE; use IEEE.STD_LOGIC_1164.all; package func_lib is function parity (input : std_logic_vector)return std_logic; end func_lib; package body func_lib is function parity (input : std_logic_vector)return std_logic is variable temp : std_logic := '0'; begin for i in input'range loop temp := temp xor input(i); end loop; return temp; end parity; end func_lib; function declaration function definition Example in VHDL_AF.zip

44. Example in VHDL_AF.zip library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use work.func_lib.all; entity VHDL_test is Port ( data_in : in std_logic_vector(7 downto 0); data_out : out std_logic_vector(3 downto 0); index_out: out std_logic_vector(3 downto 0); clk : in std_logic; reset : in std_logic); end VHDL_test; architecture Behavioral of VHDL_test is begin data_out <= "000" & parity(data_in); end Behavioral;

45. label: for parameter in range generate concurrent statements end generate label; The for … generate construction can be used to instantiate an array of component, for example: generic ( R : integer := 3; -- other generic statements ); --............................ FSM_reg:-- register of an FSM for i in 0 to R-1 generate REG:FDC port map (CS(i),clk,rst,NS(i)); end generate FSM_reg; REG next state (NS) current state (CS) D Flip-Flop with Asynchronous Clear from Xilinx library clk rst

46. library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity ROM_FSM is generic (L : integer := 8; R : integer := 3; N : integer := 4; G : integer := 2); Port ( clk: in std_logic; rst: in std_logic; X: in STD_LOGIC_VECTOR(L-1 downto 0); Y: out STD_LOGIC_VECTOR(N-1 downto 0)); end ROM_FSM; This is a top level specification of a reprogrammable finite state machine (RFSM) See complete example in the tutorial about RFSMs

47. architecture Behavioral of ROM_FSM is component FDC generic (INIT : bit := '1'); port (Q : out STD_ULOGIC; C : in STD_ULOGIC; CLR : in STD_ULOGIC; D : in STD_ULOGIC); end component; component level is generic (L : integer := 8; R : integer := 3; N : integer := 3); Port ( X: in STD_LOGIC_VECTOR(L-1 downto 0); ds: in STD_LOGIC_VECTOR(R-1 downto 0); T: out STD_LOGIC_VECTOR(N-1 downto 0)); end component;

48. signal m_out : std_logic_vector(G downto 1); type between_levels is array (G downto 0) of std_logic_vector (R-1 downto 0); signal dummy_state : between_levels; begin Y <= '0' & dummy_state(0); FSM_reg: for i in 0 to R-1 generate REG:FDC port map (dummy_state(0)(i),clk,rst,dummy_state(G)(i)); end generate FSM_reg; FSM_CC: for i in 1 to G generate level_PM: level generic map(L=>8,R=>3,N=>3) port map(X,dummy_state(i-1),dummy_state(i)); end generate FSM_CC; end Behavioral;

49. entity entity_name is generic (generic_list); port (declarations); end entity_name; entity Gen_Mux is generic (L : integer := 8; R : integer := 3); Port ( SEL: in STD_LOGIC_VECTOR(R-1 downto 0); X : in STD_LOGIC_VECTOR(L-1 downto 0); MUX_OUT : out STD_LOGIC); end Gen_Mux; component component_name is generic (generic_list); port (declarations); end component; instance_label: component_name generic map (association_list); port map (association_list); component Gen_Mux is generic (L : integer; R : integer); Port (SEL : in STD_LOGIC_VECTOR(R-1 downto 0); X: in STD_LOGIC_VECTOR(L-1 downto 0); MUX_OUT: out STD_LOGIC); end component; MUX: Gen_Mux generic map(L=>8,R=>3) port map(link,X,MUX_OUT); Generics enable us to pass instance specific information into an entity

50. library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity Gen_Mux is generic (L : integer := 8; R : integer := 3); Port ( SEL: in STD_LOGIC_VECTOR(R-1 downto 0); X: in STD_LOGIC_VECTOR(L-1 downto 0); MUX_OUT: out STD_LOGIC); end Gen_Mux; architecture Behavioral of Gen_Mux is begin MUX_OUT <= X(conv_integer(SEL)); end Behavioral; -- default value

51. library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity ROM is generic (N : integer := 3; deep : integer := 8; R : integer := 3); port ( a : in std_logic_vector(R-1 downto 0);-- address spo : out std_logic_vector(N-1 downto 0)); -- data end ROM; architecture Behavioral of ROM is type ram_type is array (deep-1 downto 0) of std_logic_vector (N-1 downto 0); constant ROM : ram_type := ("111","110","101","011","100","010","001","000"); begin spo <= ROM(conv_integer(a)); end Behavioral;

52. library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity Prog_Mux is generic (L : integer := 8; R : integer := 3); Port ( state: in STD_LOGIC_VECTOR(R-1 downto 0); X: in STD_LOGIC_VECTOR(L-1 downto 0); MUX_OUT: out STD_LOGIC); end Prog_Mux; gen_mux rom link X state MUX_OUT

53. architecture Behavioral of Prog_Mux is component Gen_Mux is generic (L : integer; R : integer); Port ( SEL: in STD_LOGIC_VECTOR(R-1 downto 0); X: in STD_LOGIC_VECTOR(L-1 downto 0); MUX_OUT: out STD_LOGIC); end component; component ROM is generic (N : integer; deep : integer := 8; R : integer); port ( a : in std_logic_vector(R-1 downto 0); spo : out std_logic_vector(N-1 downto 0)); end component; signal link : std_logic_vector(R-1 downto 0); begin MUX : Gen_Mux generic map(L=>8,R=>3) port map(link,X,MUX_OUT); MUX_ROM : ROM generic map(N=>3,deep=>8,R=>3) port map(state,link); end Behavioral;

54. if condition1 then sequential_ statements elsif condition2 then sequential_statements else sequential_statements end if; process(clk, rst) variable tmp, ind: integer; begin if rst= '1' then tmp:=0; ind :=0; elsif falling_edge(clk) then if rs232in = '0' then ind := 1; end if; if (tmp >= 1) then if (tmp <= 8) then LCD_symbol(tmp-1) <= rs232in; end if; if ind = 1 then tmp := tmp + 1; end if; if (tmp >= 9) and (rs232in = '1') then tmp := 0; ind := 0; end if; result <= LCD_symbol; end process;

55. if condition1 then sequential_ statements elsif condition2 then sequential_statements else sequential_statements end if; process (CLK, RESET) begin if RESET='1' then COUNT <= "0000"; elsif CLK='1' and CLK'event then if CE='1' then if LOAD='1' then COUNT <= DIN; else if DIR='1' then COUNT <= COUNT + 1; else COUNT <= COUNT - 1; end if; end process; counter example from ISE 5.2 template 12345

56. library library_name ; library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; The library WORK do not have to be declared permits to use the respective packages of the library IEEE

57. Literals are used in expressions index_out <= conv_std_logic_vector(2#01_10#,4); -- the result is 6 base can be from 2 to 16 numeric literal separator (underscore) is ignored in the literal and it permits to use more readable form index_out <= B"1_001";-- the result is 9 bit vector, for example, std_logic_vector base might be binary (B or b), octal (O or o) or hexadecimal (X or x) constant line1: string(1 to 8):= " Index:" & CR; non-printing character can be concatenated Arrays of characters, such as strings and bit vectors are enclosed by quotes

58. Literals are used in expressions constant line1: string(1 to 8):= " Index: "; constant line2: string(1 to 10):= " Result: "; index_out <= conv_std_logic_vector(2#01_10#,4); -- the result is 6 index_out <= conv_std_logic_vector(3#00_21#,4); -- the result is 7 index_out <= conv_std_logic_vector(9#00_10#,4); -- the result is 9 index_out <= conv_std_logic_vector(12#00_10# - 10#00_10#,4); -- the result is 2 index_out <= B"1_001";-- the result is 9 index_out <= abs(O"31");-- the result is 9 (011 001) index_out <= abs(x"F_34"); -- the result is 4 (1111 00110100) see VHDL code for the block lcd from slide 3

59. Names are used for identifiers. variable tmp32, ind: integer; Names may be composed of letters, digits and underscore. signal my_sig2 : std_logic_vector; Case is not significant, i.e. uppercase and lowercase letters are considered to be the same. variable temp : std_logic := '0'; or variable TeMp : std_logic := '0'; Names must begin with a letter. signal M3d : integer; VHDL reserved words cannot be used as names. entity, wait, exit, …..

60. on off For example: process(data_in) variable index : integer; begin index := 0; index_out '0'); for index in data_in'reverse_range loop if index = 5 then exit; elsif index = 2 then next; else if data_in(index)= '1' then index_out <= conv_std_logic_vector(index,4); end if; end loop; end process; on off index_out keeps the number of the last DIP switch “on” from left to right (except DIP switch 2) index_out = 1 0 1 2 next; next loop_label; next when condition; the number of the last DIP switch, which is checked is 4

61. process(data_in) variable index : integer; begin index := 0; index_out '0'); for index in data_in'reverse_range loop next when index = 3; if index = 5 then exit; else if data_in(index)= '1' then index_out <= conv_std_logic_vector(index,4); end if; end loop; end process; index_out keeps the number of the last DIP switch “on” from left to right (except DIP switch 3) next; next loop_label; next when condition; The number of the last DIP switch, which is checked is 4

62. on off null; The null statement performs no action process(data_in) begin case data_in(1 downto 0) is when "00" => index_out <= "0" & (data_in(7 downto 5) and data_in(4 downto 2)); when "01" => index_out <= "0" & (data_in(7 downto 5) or data_in(4 downto 2)); when "10" => index_out <= "0" & (data_in(7 downto 5) xor data_in(4 downto 2)); when others => null; end case; end process; operation: “00” – AND; “01” – OR; “10” - XOR 0 1 2 - 4 operand 2 5 - 7 operand 1 null indicates no action when the code operation is equal to “11”

63. architecture Behavioral of VHDL_test is signal for_op1,for_op2,result : integer; --..................................... begin for_op1 <= conv_integer(data_in(7 downto 5)); for_op2 <= conv_integer(data_in(4 downto 2)); process(data_in) begin case data_in(1 downto 0) is when "00" => result <= for_op1 + for_op2; when "01" => result <= for_op1 - for_op2; when "10" => result <= for_op1 * for_op2; when others => null; end case; end process; index_out <= conv_std_logic_vector(result,4); used in expressions Logical operators: and, or, nand, nor, xor, not Arithmetical operators: + - addition, -- subtraction, * - multiplication, / - division performs subtraction over integers with sign (which is the most significant bit)

64. for_op1 <= conv_integer(data_in(7 downto 2)); process(data_in) begin case data_in(1 downto 0) is when "00" => result <= for_op1 / 2; when "01" => result <= for_op1 / 4; when "10" => result <= for_op1 / 8; when others => null; end case; end process; index_out <= conv_std_logic_vector(result,4); used in expressions Arithmetical operators: + - addition, -- subtraction, * - multiplication, / - division

65. process(data_in) begin if data_in(0) < data_in(1) then index_out(0) <= '1'; else index_out(0) <= '0'; end if; if data_in(2) > data_in(3) then index_out(1) <= '1'; else index_out(1) <= '0'; end if; if data_in(4) <= data_in(5) then index_out(2) <= '1'; else index_out(2) <= '0'; end if; if data_in(6) >= data_in(7) then index_out(3) <= '1'; else index_out(3) <= '0'; end if; end process; used in expressions Relational operators: < - less than, > - greater than, <= - less than or equal to, >= - grater than or equal to & - concatenation operator For example: index_out <= “01” & “10”; Result:index_out = “0110”

66. package Package_Name is declarations end Package_Name; package func_lib is function parity (input : std_logic_vector) return std_logic; end func_lib; 23 4 1567

67. library IEEE; use IEEE.STD_LOGIC_1164.all; package is type is record : std_logic_vector( 7 downto 0); : std_logic; end record; constant : time := ns; constant : integer := ; function (signal : in ) return ; procedure ( : in ); end ; package Package_Name is declarations end Package_Name;

68. package body is -- Example 1 function (signal : in ) return is variable : ; begin := xor ); return ; end ; -- Example 2 function (signal : in ; signal : in ) return is begin if ( = '1') then return ; else return 'Z'; end if; end ; -- Procedure Example procedure ( : in ) is begin end ; package body Package_Name is subprogram_bodies end Package_Name;

69. procedure procedure_name (parameter_list) is declarations begin sequential_statements end procedure_name architecture bhv of lcd is --..................... procedure dec4_bcd (signal dec4 : in std_logic_vector(3 downto 0); signal bcdM : out std_logic_vector(3 downto 0); signal bcdL : out std_logic_vector(3 downto 0)) is begin case dec4 is when "0---" | "100-" => bcdM '0'); bcdL <= dec4; when others => bcdM <= "0001"; bcdL <= dec4 + "0110"; end case; end dec4_bcd; --..................... begin --..................... This procedure converts 4 bit binary number to 8 bit BCD number, where bcdL is the less significant BCD digit and bcdM is the most significant BCD digit

70. The considered procedure is used in the lcd.vhd file (see slide 2) Index: 00 The procedure might be tested with the aid of the following process in the vhdl_test file (see slide 2) process(clk,reset) variable tmp : std_logic_vector(3 downto 0); begin if reset = '1' then tmp := "0000"; elsif rising_edge(clk) then tmp := tmp+1; end if; index_out <= tmp; end process; 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 00 … clock frequency is equal 1-2 Hz

71. process ( ) declarations begin sequential_statements end process I_am_label: process(clk) variable tmp : std_logic_vector(3 downto 0); begin if rising_edge(clk)then tmp := tmp+1; index_out <= tmp; end if; end process I_am_label; I_am_label: process variable tmp : std_logic_vector(3 downto 0); begin wait until rising_edge(clk); tmp := tmp+1; index_out <= tmp; end process I_am_label; Similar processes The sensitivity_list is a set of signals. Any change in these signals causes the process to be activated The sensitivity_list of a combinational process (for a combinational circuit) must contain all the input signals and the process must update all the output signals

72. type’(expression); index_out <= std_logic_vector'("0000") + example2; architecture Behavioral of VHDL_test is signal example2 : integer range 0 to 15 := 11; --................................... The type of a qualified expression is explicitly indicated Qualified expressions may be useful when overloaded functions or procedures are called. It permits to indicate the correct version by providing proper types of the arguments

73. used in architecture signal signal_name : type; signal signal_name : type := initial_value; architecture Behavioral of VHDL_test is signal example1 : std_logic_vector(3 downto 0) := "1010"; signal example2 : integer range 0 to 15 := 11; signal example3 : std_logic_vector(0 to 3) := "1100"; --............................................. Any signal that is driven by more than one process (concurrent statement or component) must be declared with a resolved type, i.e. std_logic or std_logic_vector Signals cannot be declared in a process, a function or a procedure (but they can be formal parameters of a function or a procedure)

74. used in architecture signal_name <= expression; signal_name <= expression after delay; delay is usually ignored by synthesis tools result <= for_op1 + for_op2; for_op1 <= conv_integer(data_in(7 downto 2)); result <= for_op1 * for_op2 after 10 ns; sum <= op1 xor op2 after 20 ms;

75. used in architecture signal_name <= expression1 when condition1 else expression2 when condition2 else expression3; result <= for_op1 + for_op2 when data_in(1 downto 0) = "00" else for_op1 - for_op2 when data_in(1 downto 0) = "01" else for_op1 * for_op2 when data_in(1 downto 0) = "10" else result; the final else must be used each condition is a Boolean expression

76. used in architecture with expression select signal_name <= expression1 when value1, expression2 when value2, expression3 when others; with data_in(1 downto 0) select result <= for_op1 + for_op2 when "00", for_op1 - for_op2 when "01", for_op1 * for_op2 when "10", result when others; The rules are the same as for the case statement (including specification of a range)

77. used in process, procedure signal_name <= expression; signal_name <= expression after delay; process (CLK)begin if CLK'event and CLK='1' then if (LOAD='1') then REG <= LOAD_DATA; else REG <= DIN & REG(3 downto 1); end if; DOUT <= REG(0); end process; Loadable shift register from ISE 5.2 synthesis template Sequential signal assignments will be done only when the respective process suspends. If there are several assignments to the same signal the last one takes affect --.............. A <=B; A<= C+D; end process;

78. subtype tiny is integer range 0 to 63; subtype part_of_std is std_logic range '1' to '-'; subtype sybtype_name is base_type range range_values; 1)'1'- logical 1 2)'0'- logical 0 3)'H' – weak 1 4)'L' – weak 0 5)'X' – unknown 6)'U' – uninitialized 7)'Z' – high impedance 8)'-' – don't care 9)'W' – weak unknown std_logic values subtype word8 is std_logic_vector (8 downto 1); type serial_pac is array (0 to 8) of word8; constant line_RS : serial_pac := ( x"1B", --delete display x"44", --delete display x"4C", --delete display x"1B", --draw line (ESC) x"47", --draw line (code of this operation) x"30",-- x1 left point x"15",-- y1 upper point x"E6",-- x2 right point x"72");-- y2 bottom point

79. type type_name is type_specification; Pre-defined in VHDL scalar types are: integer, real, bit, Boolean, character subtype word8 is std_logic_vector (8 downto 1); type serial_pac is array (0 to 8) of word8; constant line_RS : serial_pac := ( x"1B", --delete display x"44", --delete display x"4C", --delete display x"1B", --draw line (ESC) x"47", --draw line (code of this operation) x"30",-- x1 left point x"15",-- y1 upper point x"E6",-- x2 right point x"72");-- y2 bottom point type positive_integers is range 0 to integer'high; type FSM_states is (start, increment, save, decrement,repeat); signal state : FSM_states; signal p_i : positive_integers;

80. type type_name is type_specification; type serial_package is record start_bit : std_logic; data_bits : std_logic_vector (7 downto 0); parity_bit : std_ulogic; stop_bit : std_logic; number : integer range 0 to 127; end record; signal my_sp : serial_package; my_sp.number <= 10; my_sp.start_bit <= '1'; my_sp.data_bits '1'); Record type objects can be assigned using aggregates (see section A - aggregates) Assigning individual fields.

81. use IEEE.NUMERIC_STD.ALL;-- for to_unsigned --................................... index_out <= conv_std_logic_vector(index,4); for_op1 <= conv_integer(data_in(7 downto 5)); index_out <= std_logic_vector(to_unsigned(character'pos('6'),4)); index_out <= std_logic_vector(to_unsigned(character'pos(line2(1)), 8)); target_type(expression)function(expression) Only closely related expression might be converted type my_array is array (0 to 5) of std_logic; signal mem1 : my_array; signal mem2 : std_logic_vector (0 to 5); --mem1 <= mem2; error mem1 <= my_array(mem2);-- OK mem2 <= std_logic_vector(mem1);-- OK examples:

82. For conversion between non closely related types a user-defined function can be used, for example: architecture Behavioral of VHDL_test is --..................... function Bollean_to_std_logic(input : Boolean) return std_logic is begin if input then return '1'; else return '0'; end if; end Bollean_to_std_logic; --..................... begin index_out <= "000" & Bollean_to_std_logic(true);

83. used in process, procedure, function variable variable_name : type; variable variable_name : type := initial_value; process(clk,reset) variable tmp : std_logic_vector(3 downto 0); begin if reset = '1' then tmp := "0000"; elsif rising_edge(clk) then tmp := tmp+1; end if; index_out <= tmp; end process; function parity (input : std_logic_vector) return std_logic is variable temp : std_logic := '0'; begin for i in input'range loop temp := temp xor input(i); end loop; return temp; end parity; variable my_int : integer range 25 downto 0; variable line : string(1 to 7) := "Index: "; variable for_test : Boolean := false; variable flag : std_logic := '1'; variable positive_integer : integer range 0 to integer'high;

84. used in process, procedure, function variable_name := expression; tmp := conv_integer(data_in); tmp := tmp+1; temp := temp xor input(i); variable assignment is done immediately Assignment can be done from signals to variables and vice versa (type match has to be provided) -- possible assignments in the process my_proc index_out <= tmp; tmp := index_out; -- declared as external port of an entity index_out : buffer std_logic_vector(3 downto 0); -- declared in a process my_proc variable tmp : std_logic_vector(3 downto 0);

85. wait until condition; wait; wait for time; wait on list_of_signals These wait statements are usually not supported by synthesis tools process variable tmp : std_logic_vector(3 downto 0); begin wait until rising_edge(clk); tmp := tmp+1; index_out <= tmp; end process; It is not allowed to use wait statement in any process with a sensitivity list

86. while condition loop sequential statements end loop; loop sequential statements end loop; on off For example: on off entity VHDL_test is Port ( index_out: out std_logic_vector(3 downto 0); --........................................ process(data_in) variable index : integer range 0 to 5; begin index := 0; index_out '0'); loop exit when index = 5; if data_in(index)= '1' then index_out <= conv_std_logic_vector(index,4); end if; index := index + 1; end loop; end process; index_out keeps the number of the last DIP switch “on” from left to right the number of the last DIP switch, which is checked is 4 index_out = 2 0 1 2

87. while condition loop sequential statements end loop; loop sequential statements end loop; process(data_in) variable index : integer range 0 to 5; begin index := 0; index_out '0'); while index /= 5 loop if data_in(index)= '1' then index_out <= conv_std_logic_vector(index,4); end if; index := index + 1; end loop; end process; Repeat the loop until index is not equal to 5

88. All the other sections (i.e. sections without such indication) have examples in the project VHDL.zip Example in VHDL_AF.zip Sections of the tutorial that have examples in the projects VHDL_AF.zip, VHDL_ASS.zip have the following indication: OR Example in VHDL_ASS.zip

89. -- uncomment for [W while statement] --process(data_in) --variable index : integer range 0 to 5; --begin --index := 0; --index_out '0'); --while index /= 5 loop --if data_in(index)= '1' then --index_out <= conv_std_logic_vector(index,4); --end if; --index := index + 1; --end loop; --end process; -- uncomment for [W while statement] process(data_in) variable index : integer range 0 to 5; begin index := 0; index_out '0'); while index /= 5 loop if data_in(index)= '1' then index_out <= conv_std_logic_vector(index,4); end if; index := index + 1; end loop; end process; ---- elsif index = 2 then next; Lines with double comment indication (i.e. – and --) can be alternatively used for the same example, i.e. for one step these lines are not needed, but for the other steps they have to be uncommented. All the required details are presented in this tutorial Some examples, such as that are useful for sections [B blocks], [C case] and [C component], can be found in another tutorial (a reference to the particular tutorial is provided)