1. HPEC 09 -1 HN 9/23/2009 MIT Lincoln Laboratory RAPID: A Rapid Prototyping Methodology for Embedded Systems Huy Nguyen, Thomas Anderson, Stuart Chen, Ford Ennis, Michael Eskowitz, Andy Heckerling, Tanya Kortz, George Lambert, Larry Retherford, Michael Vai HPEC 2009 23 September 2009 This work is sponsored by the Department of the Air Force under Air Force contract FA8721-05-C-0002. Opinions, interpretations, conclusions and recommendations are those of the author and are not necessarily endorsed by the United States Government.

2. MIT Lincoln Laboratory HPEC 09 2 HN 9/23/2009 RAPID - Rapid Advanced Processor In Development Custom VME / VPX MicroTCA COTS Boards Control Sig. Proc. Capture Composable Processor Board Form Factor Selection Design FPGA Container Infrastructure IO Known Good Designs RAPID Tiles and IP Library Main features of RAPID: Composable board design process –Custom processor composed of tiles extracted from known-good boards Form factor highly flexible –Tiles accompanied with verified firmware / software for host computer interface Container framework allowing co-design of boards and IPs –Portable FPGA Container Infrastructure with on-chip control infrastructure, off-chip memory access, and host computer interface –Surrogate board can be used while target board(s) are being designed or purchased System Architecture

3. MIT Lincoln Laboratory HPEC 09 3 HN 9/23/2009 Composable Board Design Flow Known Good Boards Extract circuit block of interest (Known Good Circuit) Tile Re-use Library Hierarchical Composite “Known Good Tile” Physical Design Reuse tool RAPID Design Board Verify Reduces time 50% to 66% as well as increases probability of first-spin success Duration Approach Sche- matic LayoutManu- facture Test & Debug Total (mos.) Start from scratch3-62-41-2 7-14 Known Good Board1-3 1-2 4-10 Known Good Tiles0.5-1 1-1.5 3-5 Board design time

4. MIT Lincoln Laboratory HPEC 09 4 HN 9/23/2009 RAPID System Development 6 months head start on surrogate system –Overlapping of FPGA and board design –Standardized control interface allows smooth porting to objective system 2 months saved in system debug and integration –Incremental integration with local storage for data path source / sink Full capability RAPID board design ADC DIQFIRABF Packet Forming Sample Timing Control Packet Forming ADC data Processed data Analog data Timing signals Control* Data path RAPID Processor Initial capability Development Timeline *A. Heckerling, T. Anderson, H. Nguyen, et.al., An Ethernet-Accessible Control Infrastructure For Rapid FPGA Development, HPEC 2008. ~12 months ~13-14 months