2. ICC Module 3 Lesson 1 – Computer Architecture 1 / 13 © 2015 Ph. Janson Information, Computing & Communication Computer Architecture Clip 2 – Von Neumann Architecture School of Computer Science & Communications P. Ienne (charts), Ph. Janson (commentary)

3. ICC Module 3 Lesson 1 – Computer Architecture 2 / 13 © 2015 Ph. Janson Outline ►Clip 0 – IntroductionClip 0 ►Clip 1 – Software technology – Assembler languageClip 1  Algorithms  Registers  Data instructions  Instruction numbering  Control instructions ►Clip 2 – Hardware architecture – Von Neumann’s stored program computer architectureClip 2  Data storage and processing  Control storage and processing ►Clip 3 – Hardware design – Instruction encodingClip 3 ►Harware implementation – Transistor technology  Clip 4 – Computing circuits Clip 4  Clip 5 – Memory circuits Clip 5 ►Hardware performance  Clip 6 – Logic parallelism Clip 6  Clip 7 – Architecture parallelism Clip 7 First clipPrevious clipNext clip

4. ICC Module 3 Lesson 1 – Computer Architecture 3 / 13 © 2015 Ph. Janson From algorithms to computers: Step 2 Hardware Software Sum of the n first integers Input : n Output: m s ← 0 as long as n > 0 s ← s + n n ← n – 1 m ← s Sum of the n first integers Input : r1 Output: r2 1: load r3, 0 2: jump_lte r1, 0, 6 3: add r3, r3, r1 4: add r1, r1, -1 5: jump 2 6: load r2, r3

5. ICC Module 3 Lesson 1 – Computer Architecture 4 / 13 © 2015 Ph. Janson ►An arithmetic unit to execute arithmetic instructions What do we need for computing? 3 + 2 = 5 Arithm. unit 3 2 5 add

6. ICC Module 3 Lesson 1 – Computer Architecture 5 / 13 © 2015 Ph. Janson ►Registers to record operands and results What do we need for computing? r1: 2 r2: ? r3: 3 r4: ? r5: ? 5 Registers r3 r1 2 r3 3 write read

7. ICC Module 3 Lesson 1 – Computer Architecture 6 / 13 © 2015 Ph. Janson The architectural elements for computing Arithm. unit Registers A B What to write & to read AB Op add r3, r3, r1 r3r1r3add 3 2 5 5 C C

8. ICC Module 3 Lesson 1 – Computer Architecture 7 / 13 © 2015 Ph. Janson ►Our algorithm or program needs to be recorded somewhere ►We also need to record where we are at What else do we still need? 1: loadr3, 0 2: jump_lter1, 0, 6 3: addr3, r3, r1 4: addr1, r1, -1 5: jump2 6: loadr2, r3 3: Instructions memory Line Instruction Add r3, r3, r1 Next instruction 4: Instruction pointer 4: 3: write read

9. ICC Module 3 Lesson 1 – Computer Architecture 8 / 13 © 2015 Ph. Janson To control where we are at Instruction pointer Instructions memory Line Instruction Decoder add r3, r3, r1 r3r1r3add 3 A relatively simple circuit that separates the elements making up an instruction

10. ICC Module 3 Lesson 1 – Computer Architecture 9 / 13 © 2015 Ph. Janson ►Normally instructions are executed in sequence => add 1 to the instruction pointer To control where we are at Instruction pointer 3 + 1 4 ►But when the processor hits a jump instruction we need to force the next instruction to be some other line 5: jump 2 Instruction pointer 5 + 1 6 2 jump 3: add r3, r3, r1

11. ICC Module 3 Lesson 1 – Computer Architecture 10 / 13 © 2015 Ph. Janson The architectural elements for sequential control Instructions memory Line Instruction Decoder add r3, r3, r1 r3r1r3add Instruction pointer 3 4 + 1

12. ICC Module 3 Lesson 1 – Computer Architecture 11 / 13 © 2015 Ph. Janson Decoder The architectural elements for jump control Instructions memory Line Instruction jump_lte r1, 0, 6 r10-lte? Instruction pointer 2 + 1 3 6 6 lte! jump

13. ICC Module 3 Lesson 1 – Computer Architecture 12 / 13 © 2015 Ph. Janson Register bank A memory for more data Large data memory reading writing Where to read or write Arithm. unit Register bank A B AB Op Relatively small: only a few dozen registers What to write & to read C C

14. ICC Module 3 Lesson 1 – Computer Architecture 13 / 13 © 2015 Ph. Janson A complete processor Data memory Instruction memory Arithm. unit Register bank Instruction decoder Instruction pointer + 1