1. ECE 111, Winter 2016 http://cwcserv.ucsd.edu/~billlin/classes/ECE111/index.php Professor Bill Lin – Office hours: TBD, 4310 Atkinson Hall Lectures: – Section A00: MWF 11-11:50a, WLH 2204 – Section B00: MWF 12-12:50p, WLH 2204 – Section C00: MWF 10-10:50a, EBU1 2315 No Discussion Sections TAs: – Section A00: Yang Song and Ping Yin – Section B00: Sidharth Kodaikkal Vijayan and Pranav Marakani – Section C00: Shalini Kedlaya and Praneeth Sanapathi – Office hours: TBD – Note: You may get help from any of the 6 TAs during their office hours.

2. Projects Goal: Learn Verilog-based chip design Project 1: Simple Fibonacci Calculator – Due 1/22, Pass/No Pass Project 2: RLE Processor – Due 2/10, Pass/No Pass – Must re-do if not within 20% of average performance Final Project: SHA1 Security Processor – Due 3/17 (Wed finals week), grading on performance

3. Altera Software See Software Downloads Page http://cwcserv.ucsd.edu/~billlin/classes/ECE111/software.php which links to this: http://dl.altera.com/?edition=web Quartus Prime Lite Edition for Windows – Quartus Prime Lite Edition (earlier versions were called Quartus II) – ModelSim-Altera Edition – Arria II device support

4. Icarus Verilog Another simulator http://iverilog.icarus.com http://iverilog.icarus.com Just runs together with your testbench and prints out whatever is specified in the testbench

5. More Information No textbook for this class. Verilog information on class website. Also tutorial examples provided. This is NOT a lecture-based class. Class time used to talk about Verilog in the beginning, but mostly about project information for the rest of the quarter. Projects done in teams of 2 students.

6. Useful Altera Websites Verilog HDL Basics (50 minutes online course) http://www.altera.com/education/training/courses/OHDL1120 Demonstration Center http://www.altera.com/education/demonstrations/dem-index.html