1. CHAPTER 2 Digital Combinational Logic/Arithmetic Circuits
PGT 104 ELEKTRONIK DIGIT
CHAPTER 2
Digital Combinational
Logic/Arithmetic Circuits

2. Digital Combinational Logic/Arithmetic Circuits
Adder/Subtractor
Converters
Decoder/Encoder/Comparator
Multiplexer/ Demultiplexer
Parity Circuits
Generators
Checkers

3. Arithmetic Binary arithmetic ’s complement representation ’s complement arithmetic Hexadecimal arithmetic BCD arithmetic Arithmetic circuits Adder / subtractor bit full-adder/subtractor ICs

4. Basic Combinational Logic - AND-OR Logic
How about the truth table?

5. Basic Combinational Logic - AND-OR-Invert Logic

6. Basic Combinational Logic - Exclusive-OR logic
How about XNOR logic?

7. Complements(1) Allow the representation of negative numbers.
Complements are used in digital computers for simplifying the subtraction operation.
Two types of complement for binary numbers:
One’s complement
Two’s complement
The 1’s complement of a binary number is formed by changing 1’s to 0’s and 0’s to 1’s
Example:
The 1’s complement of is
The 1’s complement of is

8. Complements(2)
The 2’s complement of a binary number is formed by adding 1 to the 1’s complement.
2’s complement = (1’s complement) + 1

9. Complements(3) Alternative method to find 2’s complement:
Start at the right with the LSB and write the bits as they are up to including the first 1.
Do 1’s complements of the remaining bits.
Example:
The 2’s complement of is
The 2’s complement of is

10. Binary Arithmetic Operations Subtraction
Two binary numbers are subtracted by subtracting each pair of bits together with borrowing, where needed.
Example:
Borrow X: Y:

11. Combinational Arithmetic Circuits
Addition:
Half Adder (HA)
Full Adder (FA)
Carry Ripple Adders
Subtraction:
Half Subtractor
Full Subtractor
Borrow Ripple Subtractors
Subtraction using adders

12. Half Adder
Adding two single-bit binary values, X, Y produces a sum S bit and a carry out C-out bit.
This operation is called half addition and the circuit to realize it is called a half adder.
S(X,Y) = S (1,2)
S = X’Y + XY’
S = X Å Y
C-out(x, y, C-in) = S (3)
C-out = XY X 1 Y S
C-out
Half Adder Truth Table:
Inputs
Outputs X Y
Sum S
C-out
Half
Adder X Y S
C-OUT

13. Full Adder(1)
Sum S
C-in X 1 Y XY 2 3 6 7 4 5
Adding two single-bit binary values, X, Y with a carry input bit C-in produces a sum bit S and a carry out C-out bit.
Full Adder Truth Table X 1 Y S
C-out
C-in
S(X,Y, C-in) = S (1,2,4,7)
C-out(x, y, C-in) = S (3,5,6,7)
Inputs
Outputs
S = X’Y’(C-in) + X’Y(C-in)’ + XY’(C-in)’ + XY(C-in)
S = X Å Y Å (C-in)
C-in X 1 Y XY 2 3 6 7 4 5
Carry C-out
C-out = XY + X(C-in) + Y(C-in)

14. Full Adder(2) Full Adder Circuit Using AND-OR: Full Adder Sum S X X’ Y
X’Y’C-in
XY’C-in’
Sum S
X’YC-in’
XYC-in X’ X Y’ Y
C-in
C-in’ X X’ Y Y’
C-in
C-in’
Full
Adder X Y S
C-in
C-out XY
YC-in
C-out
XC-in X Y
C-in

15. Full Adder(3) Full Adder Circuit Using XOR: Full Adder C-out Sum S X Y
YC-in
C-out
XC-in X Y
C-in
Sum S
Full
Adder X Y S
C-in
C-out

16. n-bit Carry Ripple Adders
An n-bit adder used to add two n-bit binary numbers can built by connecting in series n full adders.
Each full adder represents a bit position j (from 0 to n-1).
Each carry out C-out from a full adder at position j is connected to the carry in C-in of the full adder at the higher position j+1.
The output of a full adder at position j is given by:
Sj = Xj Å Yj Å Cj
Cj+1 = Xj . Yj + Xj . Cj + Y . Cj
In the expression of the sum Cj must be generated by the full adder at the lower position j-1.
The propagation delay in each full adder to produce the carry is equal to two gate delays = 2 D
Since the generation of the sum requires the propagation of the carry from the lowest position to the highest position , the total propagation delay of the adder is approximately:
Total Propagation delay = 2 nD

17. 4-bit Carry Ripple Adder
X3X2X1X0
S3 S2 S1 S0
C-in
C-out C4
Y3Y2Y1Y0
C0 =0
Inputs to be added
Sum Output
Adds two 4-bit numbers:
X = X3 X2 X1 X0
Y = Y3 Y2 Y1 Y0
producing the sum S = S3 S2 S1 S0 ,
C-out = C4 from the most significant
position j=3
Total Propagation delay = 2 nD = 8D
or 8 gate delays
Full
Adder X1 Y1 S1
C-in
C-out X0 Y0 S0
C0 =0 X2 Y2 S2 X3 Y3 S3 C1 C2 C3 C4
Data inputs to be added
Sum output

18. Larger Adders Example: 16-bit adder using 4, 4-bit adders
Adds two 16-bit inputs X (bits X0 to X15), Y (bits Y0 to Y15) producing a 16-bit Sum S (bits S0 to S15) and a carry out C16 from most significant position.
4-bit
Adder
C-in
C-out
C0 =0 C4 C8
C12
C16
Data inputs to be added X (X0 to X15) , Y (Y0-Y15)
Sum output S (S0 to S15)
Y3Y2Y1Y0
X3X2X1X0
S3 S2 S1 S0
Propagation delay for 16-bit adder = 4 x propagation delay of 4-bit adder
= 4 x 2 nD = 4 x 8D = 32 D
or gate delays

19. Negative Binary Number Representations
Signed-Magnitude Representation:
For an n-bit binary number:
Use the first bit (most significant bit, MSB) position to
represent the sign where 0 is positive and 1 is negative.
Ex: =
Remaining n-1 bits represent the magnitude which may range from:
-2(n-1) to 2(n-1) – 1
This scheme has two representations for 0; i.e., both positive and negative 0: for 8 bits: ,
Arithmetic under this scheme uses the sign bit to indicate the nature of the operation and the sign of the result, but the sign bit is not used as part of the arithmetic.
Sign
Magnitude

20. Half Subtractor X 1 Y D B-out
Subtracting a single-bit binary value Y from anther X (I.e. X -Y ) produces a difference bit D and a borrow out bit B-out.
This operation is called half subtraction and the circuit to realize it is called a half subtractor. X 1 Y D
B-out
Half Subtractor Truth Table:
Inputs
Outputs
D(X,Y) = S (1,2)
D = X’Y + XY’
D = X Å Y
B-out(X, Y) = S (1)
B-out = X’Y X Y
Difference D
Half
Subtractor X Y D
B-OUT
B-out

21. Full Subtractor(1)
Difference D
B-in X 1 Y XY 2 3 6 7 4 5
Subtracting two single-bit binary values, Y, B-in from a single-bit value X produces a difference bit D and a borrow out B-out bit. This is called full subtraction.
Full Subtractor Truth Table: X 1 Y D
B-out
B-in
Inputs
Outputs
D = X’Y’(B-in) + X’Y(B-in)’ + XY’(B-in)’ + XY(B-in)
D = X Å Y Å (B-in)
Borrow B-out
B-in X 1 Y XY 2 3 6 7 4 5 1 1 1 1
B-out = X’Y + X’(B-in) + Y(B-in)
S(X,Y, B-in) = S (1,2,4,7)
B-out(x, y, B-in) = S (1,2,3,7)

22. Full Subtractor(2) Full Adder Circuit Using AND-OR Full Subtractor
X’Y’B-in
XY’B-in’
Difference D
X’YB-in’
XYB-in X’ X Y’ Y
B-in
B-in’ X X’ Y Y’
B-in
B-in’
X’Y
YB-in
B-out
X’B-in X’ Y
B-in
Full
Subtractor X Y D
B-in
B-out
Full Adder Circuit Using AND-OR

23. Full Subtractor(3) Full Subtractor Circuit Using XOR Full SubtractorY
B-in
Difference D
Full
Subtractor X Y D
B-in
B-out
X’Y
YB-in
B-out
X’B-in X’ Y
B-in
Full Subtractor Circuit Using XOR

24. n-bit Subtractors
An n-bit subtractor used to subtract an n-bit number Y from another n-bit number X (i.e X-Y) can be built in one of two ways:
By using n full subtractor and connecting them in series, creating a borrow ripple subtractor:
Each borrow out B-out from a full subtractor at position j is connected to the borrow in B-in of the full subtractor at the higher position j+1.
By using an n-bit adder and n inverters:
Find two’s complement of Y by:
Inverting all the bits of Y using the n inverters.
Adding 1 by setting the carry in of the least significant position to 1
The original subtraction (X - Y) now becomes an addition of X to two’s complement of Y using the n-bit adder.

25. 4-bit Borrow Ripple Subtractor
X3X2X1X0
D3 D2 D1 D0
B-in
B-out B4
Y3Y2Y1Y0
B0 =0
Inputs
Difference Output D
Subtracts two 4-bit numbers:
Y = Y3 Y2 Y1 Y0 from
X = X3 X2 X1 X0
Y = Y3 Y2 Y1 Y0
producing the difference D = D3 D2 D1 D0 ,
B-out = B4 from the most significant
position j=3
Full
Subtractor X1 Y1 D1
B-in
B-out X0 Y0 D0
B0 =0 X2 Y2 D2 X3 Y3 D3 B1 B2 B3 B4
Data inputs to be subtracted
Difference output D

26. 4-bit Subtractor Using 4-bit Adder
Inputs to be subtracted
Y3 Y2 Y1 Y0
X3 X2 X1 X0
4-bit
Adder C4
C-out
C-in
C0 = 1
S S2 S S0
D D2 D1 D0
Difference Output

27. Examples:
Add the two 4-bit binary numbers A = 1101 and B = Then show that the parallel binary adder adds the two numbers correctly.
Use 2’s compliment addition to subtract 12 from 25. Then draw subtraction process by using a binary adder.
Determine the binary output for the parallel binary adder for the inputs shown.
Full
Adder 1 S1
C-in
C-out S0
C0 = gnd S2 S3 C1 C2 C3 C4
Sum output

28. Next lecture….
Converters ~ Comparator ~ Decoder ~ Encoder ~ Code converter